hi5766 Intersil Corporation, hi5766 Datasheet
hi5766
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hi5766 Summary of contents
Page 1
... TM Data Sheet 10-Bit, 60MSPS A/D Converter The HI5766 is a monolithic, 10-bit, analog-to-digital converter fabricated in a CMOS process designed for high speed applications where wide bandwidth and low power consumption are essential. Its 60MSPS speed is made possible by a fully differential pipelined architecture with an internal sample and hold ...
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... Functional Block Diagram S/H + ∑ ∑ AGND CC 2 HI5766 BIAS STAGE 1 2-BIT 2-BIT FLASH DAC STAGE 8 2-BIT 2-BIT FLASH DAC STAGE 9 2-BIT FLASH DV DGND1 (OPTIONAL) CC1 REF REF CLK CLOCK DFS OE DV CC2 D9 (MSB DIGITAL DELAY ...
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... V - Negative Analog Input Bias Voltage Output AGND Analog Ground Analog Supply (+5.0V Digital Output Enable Control Input. 3 HI5766 HI5766 V + (7) REF V - (8) REF (LSB) (28 (27 (26) D2 AGND (12) D2 AGND (6) (25 DGND (24 DGND1 (2) ...
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... Operating Conditions Temperature Range HI5766KCB (Typ CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... OL Output Three-State Leakage Current Output Logic High Voltage Output Logic Low Voltage Output Three-State Leakage Current Output Capacitance, C OUT 5 HI5766 = DV = 5.0V 3.0V 2.5V; V CC1 CC2 REF Differential Analog Input; Typical Values are Test Results TEST CONDITIONS ...
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... Supply Current Power Dissipation Offset Error Sensitivity, ∆V OS Gain Error Sensitivity, ∆FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. 6 HI5766 = DV = 5.0V 3.0V 2.5V; V CC1 CC2 REF Differential Analog Input; Typical Values are Test Results at 25 ...
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... N LAT FIGURE 1. HI5766 INTERNAL CIRCUIT TIMING 1. 2.4V DATA 0.5V FIGURE 2. INPUT-TO-OUTPUT TIMING ...
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... NOTE: SFDR depicted here does not include any harmonic distortion. FIGURE 5. -2HD, -3HD, -THD AND SFDR vs INPUT FREQUENCY DUTY CYCLE (%, t H FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE CLOCK DUTY CYCLE 8 HI5766 MSPS 100 9 f ...
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... SFDR 60 -2HD 55 -THD 50 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2. (V) REF FIGURE 13. -2HD, -3HD, -THD AND SFDR NOT DRIVEN) REF 9 HI5766 (Continued SNR NOTE: SFDR depicted here does not include any harmonic distortion. FIGURE 10. -2HD, -3HD, -THD AND SFDR REF 51 50 ...
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... TEMPERATURE ( FIGURE 17. REFERENCE CURRENT vs TEMPERATURE 0. 17.72 MSPS S 0.85 0.80 DG 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -40 - TEMPERATURE ( C) FIGURE 19. DIFFERENTIAL GAIN/PHASE vs TEMPERATURE 10 HI5766 (Continued FIGURE 16. SUPPLY CURRENT vs SAMPLE CLOCK 9.5 9 REF 8.5 8.0 7.5 7.0 6 REF 6.0 - FIGURE 18. DATA OUTPUT DELAY vs TEMPERATURE ...
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... DC -100 Detailed Description Theory of Operation The HI5766 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 24 depicts the circuit for the front end differential-in-differential-out sample- and-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, φ ...
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... REF 12 HI5766 Analog Input, Differential Connection The analog input to the HI5766 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 25 and Figure 26) will give the best performance for the converter. ...
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... The HI5766 provides a standard high-speed interface external TTL logic families. In order to ensure rated performance of the HI5766, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5766 will only be guaranteed at , output of the conversion rates above 1 MSPS ...
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... LSBs) is noted. Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5766. A low distortion sine wave is applied to the input coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D ...
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... The ADC is tested with each tone 6dB below full scale. 15 HI5766 Transient Response Transient response is measured by providing a full scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy. Over-Voltage Recovery ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 16 HI5766 Data Latency (t ) LAT ...