EP1C20F400 Altera Corporation, EP1C20F400 Datasheet

Page 1

... Maximum user I/O pins (1) Note to Table 1: (1) This parameter includes global clock pins. Altera Corporation DS-CYCLONE-1.1 ® The Cyclone TM field programmable gate array family is based on a 1.5-V, 0.13- m, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase- ...

Page 2

... PQFP 0.5 0.5 484 1,024 22 22 34.6 34.6 Preliminary Information Tables 2 through 3). 256-Pin 324-Pin FineLine FineLine BGA BGA 249 185 185 249 233 256-Pin 324-Pin FineLine FineLine BGA BGA 1.0 1.0 289 361 Altera Corporation 400-Pin FineLine BGA 301 301 400-Pin FineLine BGA 1.0 441 21 21 ...

Page 3

... Preliminary Information Table of Contents Altera Corporation Introduction ........................................................................................................1 Features ............................................................................................................... 1 Table of Contents ...............................................................................................3 Functional Description......................................................................................4 Logic Array Blocks.............................................................................................6 Logic Elements ...................................................................................................9 MultiTrack Interconnect .................................................................................17 Embedded Memory.........................................................................................23 Global Clock Network & Phase-Locked Loops...........................................34 I/O Structure ....................................................................................................44 Power Sequencing & Hot Socketing .............................................................60 IEEE Std. 1149.1 (JTAG) Boundary Scan Support .......................................60 SignalTap II Embedded Logic Analyzer ...................................................... 65 Configuration ...

Page 4

... IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support. Figure 1 4 shows a diagram of the Cyclone EP1C12 device. Preliminary Information Altera Corporation ...

Page 5

... M4K Blocks Table 4. Cyclone Device Resources Device Columns EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Altera Corporation EP1C12 Device The number of M4K RAM blocks, PLLs, rows, and columns vary per device. Table 4 lists the resources available in each Cyclone device. M4K RAM Blocks 1 13 ...

Page 6

... Direct link interconnect from adjacent block Direct link interconnect to adjacent block 6 Figure 2 details the Cyclone LAB. LAB Local Interconnect Preliminary Information ® II Compiler places Row Interconnect Column Interconnect Direct link interconnect from adjacent block Direct link interconnect to adjacent block Altera Corporation ...

Page 7

... Direct link interconnect to left Interconnect Altera Corporation LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive an LAB’ ...

Page 8

... Figure 4. LAB-Wide Control Signals Dedicated 6 LAB Row Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect 8 labclkena2 labclkena1 labclk1 labclk2 Preliminary Information TM interconnect’s inherent low skew syncload labclr2 asyncload labclr1 or labpre Altera Corporation Figure 4 addnsub synclr ...

Page 9

... Altera Corporation The smallest unit of logic in the Cyclone architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability ...

Page 10

... These resources speed up connections between LABs while saving local interconnect resources. Interconnect” on page 17 chain connections. 10 Preliminary Information See “MultiTrack for more information on LUT chain and register Altera Corporation ...

Page 11

... Preliminary Information Altera Corporation addnsub Signal The LE’s dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either The LUT computes addition ...

Page 12

... Wide) ena (LAB Wide) aclr (LAB Wide) Preliminary Information Figure 6). The aload (LAB Wide) ALD/PRE ADATA Row, column, and Q direct link routing D Row, column, and ENA direct link routing CLRN Local routing LUT chain connection Register chain output Altera Corporation ...

Page 13

... Preliminary Information Altera Corporation Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry- ...

Page 14

... Wide) aclr (LAB Wide) LUT Carry-Out1 Preliminary Information sclear aload (LAB Wide) ALD/PRE ADATA Q D ENA CLRN Register Feedback Altera Corporation Row, column, and direct link routing Row, column, and direct link routing Local routing LUT chain connection Register chain output ...

Page 15

... Preliminary Information Altera Corporation Figure 8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions ...

Page 16

... LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to M4K memory blocks. A carry chain can continue as far as a full column. 16 LAB Carry-In Carry-In0 Carry-In1 LUT data1 data2 LUT LUT LUT Carry-Out0 Preliminary Information Sum Carry-Out1 Altera Corporation ...

Page 17

... Preliminary Information MultiTrack Interconnect Altera Corporation Clear & Preset Logic Control LAB-wide signals control the logic for the register’s clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT-gate push-back technique ...

Page 18

... Adjacent LAB can Drive onto Another C4 Column Interconnects (1) LAB's R4 Interconnect LAB Primary Neighbor LAB (2) LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks and down direction Preliminary Information R4 Interconnect Driving Right LAB Neighbor Altera Corporation ...

Page 19

... Preliminary Information Altera Corporation Cyclone devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output directly drive the fast input of the LE right below it, bypassing the local interconnect ...

Page 20

... Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE Local Interconnect Figure 11 shows the C4 interconnect connections from an Preliminary Information LE 1 Register Chain Routing to Adjacent LE's Register Input Altera Corporation ...

Page 21

... Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 11: (1) Each C4 interconnect can drive either up or down four rows. Altera Corporation Note (1) Local Interconnect Cyclone FPGA Family Data Sheet C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect ...

Page 22

... Local Interconnect Direct Link Interconnect R4 Interconnect C4 Interconnect v LE M4K RAM Block PLL Column IOE Row IOE 22 shows the Cyclone device’s routing scheme. Destination Preliminary Information Altera Corporation v v ...

Page 23

... Preliminary Information Embedded Memory Altera Corporation The Cyclone embedded memory consists of columns of M4K memory blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while EP1C12 and EP1C20 devices have two columns (see total RAM bits per density). Each M4K block can implement various types of memory with or without parity, including true dual-port, simple dual- port, and single-port RAM, ROM, and FIFO buffers ...

Page 24

... Figure 13: Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. Preliminary Information rdaddress[ ] rden q[ ] outclock outclocken outaclr q[ ] outclock outclocken outaclr Altera Corporation ...

Page 25

... Preliminary Information Altera Corporation When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. ...

Page 26

... Figure 14. Shift Register Memory Configuration Shift Register m -Bit Shift Register m -Bit Shift Register m -Bit Shift Register m -Bit Shift Register Preliminary Information Figure 14 shows the M4K memory Number of Taps w w Altera Corporation ...

Page 27

... Altera Corporation Memory Configuration Sizes The memory address depths and output widths can be configured as 4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths ...

Page 28

... Table 8: Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e and 32 modes. Figure 15. Figure 16 Preliminary Information summarizes the byte selection. Notes (1), (2) datain 18 datain 36 [8..0] [17..9] [17..9] – [26..18] – [35..27] shows the M4K block to logic array Altera Corporation [8..0] ...

Page 29

... Interconnect clock_a Figure 16. M4K RAM Block LAB Row Interface C4 Interconnects Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB M4K RAM Block Local Interconnect Region Altera Corporation alcr_a clocken_a renwe_a alcr_b 10 dataout M4K RAM Block Byte enable Control Signals ...

Page 30

... Preliminary Information shows an M4K memory block in B Data ENA Q D ENA Address ENA Write/Read Write Q D Enable Pulse ENA Generator Data Out Q D ENA 6 data [ ] B byteena [ ] B address [ ] B wren B clken B clock B Altera Corporation ...

Page 31

... A D ENA address [ ] D A ENA wren A D clken A ENA clock A Note to Figure 18: (1) All registers shown have asynchronous clear ports. Altera Corporation A Memory Block 256 16 (2) Data In Q 512 8 1,024 4 2,048 2 4,096 1 Byte Enable A Byte Enable B Q Address A Q Write/Read Write ...

Page 32

... Write Address D Q ENA Read Enable D Q ENA Write Write Enable D Q Pulse ENA Generator shows a memory block in read/write clock mode. Preliminary Information Note (1) 256 ´ 16 512 ´ 8 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 Data Out D Q ENA Altera Corporation To MultiTrack Interconnect ...

Page 33

... Figure 20. Read/Write Clock Mode in Simple Dual-Port Mode 6 LAB Row Clocks 6 data[ ] address[ ] wraddress[ ] byteena[ ] rden wren rdclken wrclken wrclock rdclock Note to Figure 20: (1) All registers shown except the rden register have asynchronous clear ports. Altera Corporation D Q ENA D Q ENA D Q ENA D Q ENA D Q ENA Write D Q ...

Page 34

... Write Enable D Q Write ENA Pulse Generator Figure 22. PLL outputs, logic array, and dual-purpose clock Figure 22 shows the various sources that drive the global clock Preliminary Information RAM/ROM 256 16 512 8 1,024 4 2,048 2 4,096 1 Data Out D Q ENA Altera Corporation To MultiTrack Interconnect ...

Page 35

... The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). (2) EP1C3 devices only contain one PLL (PLL 1). (3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. Altera Corporation Note (1) DPCLK2 8 From logic From logic ...

Page 36

... I/O clock regions. 36 23. Another multiplexer at the LAB level selects two of the six LAB Global Clock Network Clock [7..0] Preliminary Information Figure 22) for high-fanout Column I/O Region IO_CLK]5..0] LAB Row Clock [5..0] Row I/O Region IO_CLK[5..0] Figure 24 shows the Altera Corporation ...

Page 37

... LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5.. Altera Corporation Column I/O Clock Region IO_CLK[5..0] Global Clock Network 8 Column I/O Clock Region IO_CLK[5..0] PLLs Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential I/O support. Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one PLL ...

Page 38

... Preliminary Information Figure 25 PLL Support m/(n post-scale counter) Down to 156-ps increments (2), Yes 2 One differential or one single-ended VCO Phase Selection Selectable at Each PLL Output Port Post-Scale Counters ÷g0 Loop ÷g1 VCO Filter ÷e Altera Corporation shows a (1) (3) (4) Global clock Global clock I/O buffer ...

Page 39

... PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are available as regular user I/O pins. (4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. Altera Corporation ...

Page 40

... Cyclone GCLK0 GCLK1 GCLK2 post scale counter) scaling factors. The input clock is divided by a Preliminary Information GCLK3 GCLK4 GCLK5 (m/n). Each output port has a IN Altera Corporation GCLK6 GCLK7 ...

Page 41

... Preliminary Information Altera Corporation Each PLL has one pre-scale divider, n, that can range in value from 1 to 32. Each PLL also has one multiply divider, m, that can range in value from 2 to 32. Global clock outputs have two post scale G dividers for global clock outputs, and external clock outputs have an E divider for external clock output, both ranging from ...

Page 42

... The designer defines which internal clock output from the PLL should be phase-aligned to compensate for internal clock delay. No compensation mode In this mode, the PLL will not compensate for any clock networks. Preliminary Information and ground voltage CC Altera Corporation ...

Page 43

... Preliminary Information f Altera Corporation Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each PLL post-scale counter (g0, g1, e). The duty cycle setting is achieved by a low- and high- time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices ...

Page 44

... Joint Test Action Group (JTAG) boundary-scan test (BST) support Output drive strength control Weak pull-up resistors during configuration Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors in user mode Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Preliminary Information Figure 27 Altera Corporation ...

Page 45

... Preliminary Information Altera Corporation Figure 27. Cyclone IOE Structure Logic Array OE Output Combinatorial input (1) Input Note to Figure 27: (1) There are two paths available for combinatorial inputs to the logic array. Each path contains a unique programmable delay chain. The IOEs are located in I/O blocks around the periphery of the Cyclone device ...

Page 46

... Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input Interconnects I/O Block Local Interconnect io_datain[2..0] and comb_io_datain[2..0] (2) Direct Link Interconnect from Adjacent LAB io_clk[5:0] Preliminary Information 21 Data and Control Signals from Logic Array (1) 21 Row I/O Block Row I/O Block Contains up to Three IOEs Altera Corporation ...

Page 47

... Each of the three IOEs in the column I/O block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. Altera Corporation Column I/O Block IO_datain[2:0] & 21 comb_io_datain[2..0] (2) ...

Page 48

... Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out Other IOEs oe ce_in ce_out Data and aclr/preset Control Signal sclr Selection clk_in clk_out dataout Figure 31 illustrates the control signal selection. Preliminary Information 34). Figure 30 IOE Altera Corporation ...

Page 49

... Local Interconnect io_cclk Local Interconnect Altera Corporation clk_out clk_in In normal bidirectional operation, the designer can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers ...

Page 50

... Input Register PRN D Q ENA CLRN Preliminary Information V CCIO Output Pin Delay Open-Drain Output Slew Control Input Pin to Logic Array Delay Input Pin to Input Register Delay or Input Pin to Logic Array Delay Optional PCI Clamp V CCIO Programmable Pull-Up Resistor Bus Hold Altera Corporation ...

Page 51

... Preliminary Information Altera Corporation A path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays decrease input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time ...

Page 52

... Top, Bottom, Left, or Right I/O Bank Note to Figure 33: (1) Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin. 52 level is 2.5 V. Additionally, the configuration CCIO Note (1) DQ Pins DQS Pin Preliminary Information level of SSTL-2 is 2.5 V. CCIO Figure 33). Each DQS pin drives the DM Pin Altera Corporation ...

Page 53

... Preliminary Information Altera Corporation Table 13 shows the number of DQ pin groups per device. Table 13. DQ Pin Groups Device Package EP1C3 100-pin TQFP (1) 144-pin TQFP EP1C4 324-pin FineLine BGA 400-pin FineLine BGA EP1C6 144-pin TQFP 240-pin PQFP 256-pin FineLine BGA EP1C12 240-pin PQFP ...

Page 54

... DDR SDRAM and FCRAM interfacing from the I/O DQS Register Register t clk OE LE Register Register Programmable Delay Chain Global Clock Preliminary Information DQ Output LE Registers Input LE DataA Registers -90˚ clk Output LE Registers Input LE DataB Registers LE Register LE Register Adjacent LAB LEs Altera Corporation Adjacent LAB LEs Resynchronizing Global Clock ...

Page 55

... Preliminary Information Altera Corporation Programmable Drive Strength The output buffer for each Cyclone device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that the designer can control. SSTL-3 class I and II, and SSTL-2 class I and II support a minimum setting, the lowest drive strength that guarantees the I of the standard ...

Page 56

... If the designer enables this feature for an I/O pin, the pull-up resistor (typically holds the output to the V level of the output pin’s bank. 56 gives the specific sustaining current for each V Preliminary Information to prevent CCIO CCIO CCIO Altera Corporation ...

Page 57

... EP1C3 devices do not support PCI. (2) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. (3) This I/O standard is only available on output clock pins (PLL_OUT pins). Altera Corporation Advanced I/O Standard Support Cyclone device IOEs support the following I/O standards: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3 ...

Page 58

... All I/O Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS SSTL-2 Class I and II SSTL-3 Class I and II I/O Bank 4 Preliminary Information I/O Bank 3 Also Supports the 3.3-V PCI I/O Standard I/O Bank 3 Individual Power Bus pins are available as user I/O pins. REF is 3 bank can CCIO Altera Corporation for CCIO ...

Page 59

... Preliminary Information Altera Corporation LVDS I/O Pins A subset of pins in all four I/O banks supports LVDS interfacing. These dual-purpose LVDS pins require an external-resistor network at the transmitter channels in addition to 100- termination resistors on receiver channels. These pins do not contain dedicated serialization or deserialization circuitry; therefore, internal logic performs serialization and deserialization functions ...

Page 60

... CCIO Preliminary Information pins can be connected to either a 1.5-V, pins are connected to a CCIO Table 17 Output Signal 1.5 V 1 (5) ( (6) (7) (7) (7) . CCIO supply current will be slightly larger CCIO and V power supplies may be CCINT 3 (8) Altera Corporation ...

Page 61

... Preliminary Information Altera Corporation Cyclone devices support reconfiguring the I/O standard settings on the IOE through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode. Designers can use this ability for JTAG testing before configuration when some of the Cyclone pins drive or receive from other devices on the board using voltage-referenced standards ...

Page 62

... Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. Monitors internal device operation with the SignalTap II embedded logic analyzer. Preliminary Information TM download cable, or when Altera Corporation ...

Page 63

... The most significant bit (MSB the left. (2) The IDCODE’s least significant bit (LSB) is always 1. Altera Corporation The Cyclone device instruction register length is 10 bits and the USERCODE register length is 32 bits. boundary-scan register length and device IDCODE information for Cyclone devices ...

Page 64

... JSCO t Update register high impedance to valid output JSZX t Update register valid output to high impedance JSXZ Preliminary Information t t JPSU JPH t JPCO t JSH t t JSCO JSXZ Min 100 Altera Corporation t JPXZ Max Unit ...

Page 65

... Preliminary Information f SignalTap II Embedded Logic Analyzer Configuration Altera Corporation For more information on JTAG, see the following documents: Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) Jam Programming & Test Language Specification Cyclone devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std ...

Page 66

... JTAG port to configure a Cyclone device. A low-cost configuration device can automatically configure a Cyclone device at system power-up the bank where the pins reside. The bank V CCIO Preliminary Information CCIO selects whether CCIO Table 22), chosen on the basis of the Altera Corporation before ...

Page 67

... STG T Ambient temperature AMB T Junction temperature J Altera Corporation Multiple Cyclone devices can be configured in any of the three configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 22. Data Sources for Configuration Configuration Scheme Active serial Passive serial (PS) JTAG Cyclone devices are offered in both commercial and industrial grades ...

Page 68

... V (8) CCIO V = 2.375 V (8) CCIO V = 1.71 V (8) CCIO Preliminary Information Minimum Maximum 1.425 1.575 3.00 3.60 2.375 2.625 1.71 1.89 1.4 1.6 –0.5 4 CCIO 0 85 –40 100 40 40 Typical Maximum –10 10 – 150 Altera Corporation Unit Unit ...

Page 69

... Low-level output voltage OL Table 28. 2.5-V I/O Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation Conditions ( –4 to – ( Conditions V = 3.0, CCIO I = –0 3.0, CCIO ...

Page 70

... V – 0.45 CCIO (9) Minimum Maximum 1.4 0. CCIO CCIO –0.3 0.35 (9) 0.75 V CCIO (9) 0.25 Minimum Typical Maximum 2.375 2.5 250 1.125 1.25 –100 0.0 90 100 Unit 1. CCIO V 0.45 V Unit 1 0 CCIO CCIO Unit 2.625 V 550 1.375 100 mV 2.4 V 110 Altera Corporation ...

Page 71

... Parameter V Output supply voltage CCIO V Termination voltage TT V Reference voltage REF V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation Conditions Minimum 3.0 0.5 V CCIO –0 –500 A 0.9 OUT V CCIO I = 1,500 A OUT Conditions Minimum 2.375 V – 0.04 REF 1 ...

Page 72

... Typical Maximum 3.0 3.3 3.6 – 0. REF REF 1.3 1.5 1.7 + 0.2 V REF CCIO –0.3 V REF + 0 Level 2.5 V 3.3 V Min Max Min 50 70 –50 –70 300 –300 Altera Corporation Unit 0.3 V – 0 – 0.6 V Unit 0.3 V – 0 – 0.8 V Unit Max A A 500 A –500 A ...

Page 73

... Drive strength is programmable according to values in (10) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels. (11) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF. Power Consumption Timing Model Altera Corporation Note (11) Parameter /user I/O pin. REF Sheet. Table 23 may cause permanent damage to a device ...

Page 74

... LE register clock-to-output delay combinatorial LUT delay for data-in to data-out LUT t Minimum clear pulse width CLR t Minimum preset pulse width PRE t Minimum clock high or low time CLKHL Preliminary Information Preliminary Tables 40 through 43 describe the Cyclone Parameter Altera Corporation Final ...

Page 75

... Preliminary Information Altera Corporation Table 41. IOE Internal Timing Microparameter Descriptions Symbol t IOE input and output register setup time before clock SU t IOE input and output register hold time after clock H t IOE input and output register clock-to-output delay CO t Row input pin to IOE combinatorial output ...

Page 76

... Local interconnect delay LOCAL shows the memory waveforms for the M4K timing parameters Table 42. t WEREH WEREH DATACO1 doutn-1 doutn t DATACO2 doutn dout0 Preliminary Information Parameter t WERESU t t WADDRH WADDRSU din4 b1 b2 dout0 Altera Corporation a5 a6 din5 din6 b3 ...

Page 77

... Preliminary Information Altera Corporation Internal timing parameters are specified on a speed grade basis independent of device density. timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 44. LE Internal Timing Microparameters Symbol -6 Min LUT ...

Page 78

... Max Min Max Min 261 300 338 388 244 281 -8 Unit Max 5,691 ps 3,783 807 ps 5,656 Unit Max 339 ps 439 ps 318 ps Altera Corporation ...

Page 79

... Preliminary Information Altera Corporation Figure 38. External Timing in Cyclone Devices Dedicated Clock All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 59 through 63 ...

Page 80

... These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II software to verify the external timing for any pin. 80 shows the external I/O timing parameters when using global Parameter Preliminary Information Notes (1), (2) Conditions LOAD LOAD LOAD LOAD LOAD LOAD Altera Corporation ...

Page 81

... Preliminary Information Altera Corporation Tables 49 through 50 show the external timing parameters on column and row pins for EP1C3 devices. Table 49. EP1C3 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max t 2.496 INSU t 0.000 INH t 2.000 3.656 OUTCO t 5.283 XZ t 5.283 ...

Page 82

... OUTCOPLL t XZPLL t ZXPLL Tables 51 and 52: Contact Altera Applications for EP1C4 device timing parameters. Preliminary Information -7 Speed Grade -8 Speed Grade Min Max Min -7 Speed Grade -8 Speed Grade Min Max Min Altera Corporation (1) Unit Max (1) Unit Max ns ns ...

Page 83

... Preliminary Information Altera Corporation Tables 53 through 54 show the external timing parameters on column and row pins for EP1C6 devices. Table 53. EP1C6 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max t 2.432 INSU t 0.000 INH t 2.000 3.720 OUTCO t 5.347 XZ t 5.347 ...

Page 84

... Speed Grade Min Max Min 2.502 2.694 0.000 0.000 2.000 4.243 2.000 5.988 5.988 1.399 1.527 0.000 0.000 0.500 1.984 0.500 3.729 4.069 3.729 4.069 Altera Corporation Unit Max ns ns 4.845 ns 6.798 ns 6.798 2.344 Unit Max ns ns 4.666 ns 6.570 ns 6 ...

Page 85

... Preliminary Information Altera Corporation Tables 57 through 58 show the external timing parameters on column and row pins for EP1C20 devices. Table 57. EP1C20 Column Pin Global Clock External I/O Timing Parameters Symbol -6 Speed Grade Min Max t 2.226 INSU t 0.000 INH t 2.000 3.926 OUTCO t 5.553 XZ t 5.553 ...

Page 86

... Speed Grade Max Min Max 235 256 358 391 0 0 244 266 244 266 291 317 291 317 217 237 Altera Corporation Unit Unit ...

Page 87

... SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS Table 62. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part Standard LVCMOS Altera Corporation -6 Speed Grade -7 Speed Grade Min Max Min 1,105 601 137 0 1,105 740 ...

Page 88

... Speed Grade Max Min Max 2,517 2,745 1,962 2,140 1,452 1,583 1,301 1,419 3,036 3,312 2,634 2,874 1,963 2,142 2,016 2,199 1,820 1,986 Altera Corporation Unit Unit ps ps ...

Page 89

... Table 64. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part I/O Standard LVCMOS 3.3-V LVTTL 2.5-V LVTTL Altera Corporation -6 Speed Grade -7 Speed Grade Min Max Min 3,643 2,446 2,477 2,334 6,606 5,112 4,862 8,380 7,437 6,888 1,799 1,363 ...

Page 90

... Speed Grade -8 Speed Grade Min Max Min 3,362 2,433 2,902 3,362 3,362 607 Altera Corporation Unit Max Unit Max 3,668 ps 2,654 ps 3,166 ps 3,668 ...

Page 91

... Parameter Decrease input delay to On internal cells Small Medium Large Decrease input delay to On input register Increase delay to output On pin Altera Corporation Setting -6 Speed Grade Min Max 3,057 2,212 2,639 3,057 3,057 556 Maximum Input & Output Clock Rates Tables 67 and ...

Page 92

... MHz 166 MHz 304 MHz 100 MHz 100 MHz 134 MHz 134 MHz 66 MHz 231 MHz Unit Grade 304 MHz 220 MHz 213 MHz 166 MHz 304 MHz 100 MHz 100 MHz 134 MHz 134 MHz 231 MHz Altera Corporation ...

Page 93

... Preliminary Information Software Device Pin- Outs Ordering Information Altera Corporation Table 70. Cyclone Maximum Output Clock Rate for Row Pins I/O Standard LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II 3.3-V PCI (1) LVDS Note to Tables 69 70: (1) EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins ...

Page 94

... Cyclone FPGA Family Data Sheet version 1.1: ® 101 Innovation Drive Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the San Jose, CA 95134 stylized Altera logo, specific device designations, and all other words and logos that are identified as (408) 544-7000 trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...