el4581 Intersil Corporation, el4581 Datasheet
el4581
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el4581 Summary of contents
Page 1
... Outputs are composite sync, vertical sync, burst/back porch output, and odd/even output. The later operates only in inter- laced scan formats. The EL4581 provides a reliable method of determining cor- rect sync slide level by setting it to the mid-point between sync tip and blanking level at the back porch. This 50% level is determined by two internal self timing sample and hold cir- cuits that track sync tip and back porch levels ...
Page 2
... C/S, Vertical and Burst outputs are all active low - V 2. Attenuation is a function of R (PIN6). SET 3. Typical min. is 0.3V . P-P 4. Refers to threshold level of sync. tip to back porch amplitude. 2 EL4581 = 25 °C) Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C +0.5V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves ...
Page 3
... SET 3 EL4581 Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge. AC coupled composite video input. Sync tip must be at the lowest potential (Positive picture phase). Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period. ...
Page 4
... Ambient Temperature (°C) 4 EL4581 Back Porch Clamp On Time vs R SET Vertical Pulse Width vs Temperature Input Signal = 300mV P-P EL4581 Filter Characteristic Constant Delay 240ns Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 2 1.8 1.6 1.471W 1.4 1.2 1 1.136 0.8 0.6 0.4 0.2 0 ...
Page 5
... Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). 5 EL4581 FIGURE 1. ...
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... Timing Diagrams (Continued) 6 EL4581 FIGURE 2. ...
Page 7
... Timing Diagrams (Continued) 7 EL4581 FIGURE 3. FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL ...
Page 8
... V which is referenced EL4581 fixed level above the clamp voltage V initiates the timing one-shots for gating the sample and hold circuits. The sample of the sync tip is delayed by 0.8µs to enable the actual sample of 2µ taken on the optimum section of the sync ...
Page 9
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 EL4581 FIGURE 5. STANDARD (NTSC INPUT) H. SYNC DETAIL *Note: RSET must be ...