ds90cr288 National Semiconductor Corporation, ds90cr288 Datasheet
ds90cr288
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ds90cr288 Summary of contents
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... LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR288 receiver converts the four LVDS data streams back into 28 bits of CMOS/TTL data transmit clock frequency of 75 MHz, 28 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel ...
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... Pin Diagram Typical Application www.national.com DS90CR288 DS100872-22 2 DS100872-23 ...
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... T CC Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except V and (Note 1) Package Derating: DS90CR288 ESD Rating (HBM, 1.5k , 100pF) (EIAJ 200pF) −0.3V to +4V Latch Up Tolerance −0. 0.3V) CC −0. ...
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... FIGURE 2. DS90CR288 (Receiver) CMOS/TTL Output Load and Transition Times www.national.com Parameter MHz MHz MHz = 3.3V (Note 5)( Figure 25˚ RCCD), where T = Clock period. See also DS90CR287/DS90CR288A datasheet. FIGURE 1. “Worst Case” Test Pattern 4 Min Typ Max Units 2 3.5 ns 1.8 3 ...
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... AC Timing Diagrams (Continued) FIGURE 3. DS90CR288 (Receiver) Setup/Hold and High/Low Times FIGURE 4. DS90CR288 (Receiver) Clock In to Clock Out Delay FIGURE 5. DS90CR288 (Receiver) Phase Lock Loop Set Time DS100872-10 DS100872-12 DS100872-14 5 www.national.com ...
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AC Timing Diagrams FIGURE 6. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR287) www.national.com (Continued) FIGURE 7. Receiver Powerdown Delay 6 DS100872-16 DS100872-18 ...
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AC Timing Diagrams (Continued) FIGURE 8. Receiver LVDS Input Strobe Position 7 DS100872-28 www.national.com ...
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... Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 6) + ISI (Inter-symbol interference)(Note 7) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 6: Cycle-to-cycle jitter is less than 250ps at 75MHz. Note 7: ISI is dependent on interconnect length; may be zero FIGURE 9. Receiver LVDS Input Skew Margin (DS90CR287/DS90CR288A) DS90CR288 Pin Description—Channel Link Receiver Pin Name I/O No ...
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... Applications Information The DS90CR287 and DS90CR288 are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR283, DS90CR284). To upgrade from 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the V , LVDS V and PLL Transmitter input and control inputs except 3.3V TTL/ CMOS levels ...
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Applications Information FIGURE 11. CHANNEL LINK Decoupling Configuration CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is ...
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Applications Information FIGURE 12. Single-Ended and Differential Waveforms (Continued) 11 DS100872-26 www.national.com ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Order Number DS90CR288MTD Dimensions in millimeters only NS Package Number MTD56 2 ...