adel2020 Analog Devices, Inc., adel2020 Datasheet
adel2020
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adel2020 Summary of contents
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... EL2020. The ADEL2020 also features an improved disable feature. The disable time (to high output impedance) is 100 ns with guaran- teed break before make. Finally the ADEL2020 is offered in the industrial temperature range of – + both plastic DIP and SOIC package. ...
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... V p- 400 400 , Step – 3.58 MHz f = 3.58 MHz kHz – kHz kHz IN Open Loop (5 MHz) –2– dc 150 unless otherwise noted) L ADEL2020A Min Typ Max 1.5 7.5 2.0 10.0 MAX MAX 0.1 1.0 MAX 65 72 MAX 0.05 0.5 MAX 0.5 7.5 ...
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... ADEL2020AR-20 ADEL2020AR-20-REEL REV. A MAXIMUM POWER DISSIPATION 18 V The maximum power that can be safely dissipated by the ADEL2020 is limited by the associated rise in junction tem- perature. For the plastic packages, the maximum safe junction V temperature is 145 C. If the maximum is exceeded momen tarily, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the device in the “ ...
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... FREQUENCY – MHz Figure 2. Closed-Loop Gain and Phase vs. Frequency 150 , for 15 V, 910 0.1µ ADEL2020 0.1µ –V S Figure 1. Connection Diagram for A GAIN = + 150 L –45 – ±15V – ...
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... R = 499 F 60 PEAKING 681 SUPPLY VOLTAGE – ± Volts = 150 L –5– ADEL2020 –1 VCL GAIN = – PHASE V = ±15V S ±5V GAIN V = ±15V S ±5V 10 100 1000 FREQUENCY – MHz = 680 ...
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... FREQUENCY – MHz Figure 10. Closed-Loop Gain and Phase vs. Frequency + 150 , R = 750 for 15 V, 715 L F Figure 12. –3 dB Bandwidth vs. Supply Voltage, Gain = +2, R 750 +V S 0.1µF 750 7 2 ADEL2020 0.1µ –V S Figure 9. Connection Diagram for A 0 –45 = 150 L – ...
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... F 50 PEAKING 442 SUPPLY VOLTAGE – ±Volts Figure 16. –3 dB Bandwidth vs. Supply Voltage, Gain = +10 150 L –7– ADEL2020 +10 VCL GAIN = + 270 PHASE ±15V S ±5V GAIN V = ±15V S ±5V 10 100 FREQUENCY – ...
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... ADEL2020 ±15V OUTPUT LEVEL FOR 3% THD ± 100k 1M 10M FREQUENCY – Hz Figure 17. Maximum Undistorted Output Voltage vs. Frequency ±15V ± CURVES ARE FOR WORST CASE 20 CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS 10 ...
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... CMOS logic, the disable time (until the output is high impedance), is about 100 ns and the enable time (to low impedance output) is about 160 ns. Since it has an internal pull- up resistor of about the ADEL2020 can be used with open drain logic as well. In this case, the enable time is in- creased to about 1 s. ...
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... OP44 –10– HIGH SLEW RATE ( 1000 V/µs) AD810 ADEL2020 AD811 AD844 AD9617 AD9618 OP160 OP260 (Dual) SPECIFIED 0.01% SETTLING AD811 AD843 AD817 AD845 AD818 AD846 AD840 AD847 AD841 OP467 (Quad) AD842 DIFFERENCE AMPLIFIER AD830 DISABLE FEATURE AD810 OP64 OP160 ADEL2020 REV. A ...
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... PLANE NOM BSC 20-Lead Wide Body SOIC (R) Package 20 11 0.419 (10.65) 0.394 (10.00 0.512 (13.00) 0.020 (0.51 0.496 (12.60) 0.104 (2.64) 0.093 (2.36) 0.019 (0.48) 0.010 0.050 (1.27) (0.254) BSC 0.014 (0.36) 0.450 (11.43) –11– ADEL2020 0.30 (7.62) REF 0.011 ±0.003 (0.28 ±0.08) ° 15 ° 0 ° CHAMF ° 8 ° 0 0.050 (1.27) 0.016 (0.40) ...
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