AD9884 Analog Devices, AD9884 Datasheet
AD9884
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AD9884 Summary of contents
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... LCD Monitors and Projectors Plasma Display Panels Scan Converters GENERAL DESCRIPTION The AD9884A is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 500 MHz ...
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... VI 100 400 700 1 IV 1000 2.5 VI 0.8 VI –1 – Binary –2– = +3.3 V, ADC Clock Frequency = Maximum, PLL D AD9884AKS-140 Min Typ Max 8 0.5 +1.15/–1.0 LSB +1.25/–1.0 LSB 0.8 1.4 2.5 Guaranteed 0.5 1.0 280 1.5 5.0 22 23.5 25 +1.20 +1.25 +1.30 50 140 10 –0.5 +2.0 4.7 4.0 0 4.7 4.0 250 4 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9884A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD9884A Signal Type Name Function Inputs R Analog Input for RED Channel AIN G Analog Input for GREEN Channel AIN B Analog Input for BLUE Channel AIN HSYNC Horizontal Sync Input COAST Clock Generator Coast Input (Optional) 3.3 V CMOS CLAMP External Clamp Input (Optional) SOGIN ...
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... GND REV. B PIN CONFIGURATION PIN 1 IDENTIFIER AD9884A TOP VIEW PINS DOWN (Not to Scale CONNECT –5– AD9884A 102 101 100 ...
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... CKEXT External Clock Input (optional) This pin may be used to provide an external clock to the AD9884A, in place of the clock internally-generated from HSYNC. This input is enabled by programming EXTCLK to 1. When an external clock is used, all other internal functions operate normally. When unused, this pin should be tied through resistor to GROUND, and EXTCLK programmed to 0 ...
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... Tie it HIGH (to V the serial address may be set to any value from 98h to 9Fh four AD9884As may be used on the same serial bus by appropriately setting these bits. They can also be used to change the AD9884A address if a conflict is found with another device on the bus ...
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... Output from the internal 1.25 V bandgap reference. This output is intended to drive relatively light loads. It can drive the AD9884A Reference input directly, but should be externally buffered used to drive other loads as well. The absolute accuracy of this output is 4%, and the temperature coefficient is 50 ppm, which is adequate for most AD9884A applications ...
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... CONTROL REGISTER MAP The AD9884A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to write and read the control registers through the 2-line serial interface port. Table II. Control Register Map Reg Bit Default Mnemonic Function PLL Divider Control 00 7– ...
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... REDGAIN Red Channel Gain Adjust An 8-bit word that sets the gain of the RED channel. The AD9884A can accommodate input signals with a full-scale range of between 0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to an input range of 1 REDGAIN of 0 establishes an input range of 0.5 V. Note that increasing REDGAIN results in the picture having less contrast (the input signal uses fewer of the available converter codes) ...
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... HSYNC enables the external CKEXT input pin. In this mode, the PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust (PHASE) is still functional. The power-up default value is EXTCLK = 0. –11– AD9884A Clamp Signal Source Clamp Signal Polarity External Clock Select ...
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... If the transmitted slave address matches the address of the device (set by the state of the SA the AD9884A acknowledges by bringing SDA LOW on the ninth SCL pulse. If the addresses do not match, the AD9884A does not acknowledge. Table IV. Serial Port Addresses Bit 7 ...
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... Any base address higher than 0Eh will not produce an ACKnowledge signal. Data are read from the control registers of the AD9884A in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation ...
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... With a typical power dissipation of only 570 mW and an operat- ing temperature range the device requires no special environmental considerations. INPUT SIGNAL HANDLING Analog Inputs The AD9884A has three high impedance analog input pins for 100 120 140 160 the red, green, and blue channels. They will accommodate signals ranging from 0 ...
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... ESD protection diodes will conduct, and may dissipate consid- erable power if the sync source is of particularly low impedance signal is applied to the AD9884A when the IC’s power is off, then even signal can turn on the ESD protection diodes. The 1 k series resistor will protect the device from overstress in this situation as well ...
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... Considerable care has been taken in the design of the AD9884A’s clock generation circuit to minimize jitter. As indicated in Fig- ure 11 and Table VI, the clock jitter of the AD9884A is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. ...
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... VESA Monitor Timing Standards and Guidelines, September 17, 1998 *Graphics sampled at 1/2 incoming pixel rate using Alternate Pixel Sampling mode. Figure 11 illustrates the AD9884A’s jitter as a percentage of the total clock period over the range of operating frequencies. Though the jitter is very low over most of the range (less than 5% of the pixel period), the jitter increases at clock rates below 40 MHz ...
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... The HSYNC output is pipelined with the data in a fixed timing relationship between the two in all Single Channel modes. There is a pipeline in the AD9884A, which must be flushed before valid data becomes available. In all single channel modes, four data sets are presented before valid data is avail- able. In all dual channel modes, two data sets are presented before valid “ ...
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... –19– AD9884A ...
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... AD9884A RGBIN P0 P1 HSYNC PXCK HS 5 PIPE DELAY ADCCK DATACK DOUTA HSOUT RGBIN HSYNC PXCK HS 5 PIPE DELAY ADCCK DATACK DOUTA HSOUT Figure 19. Single Channel Mode, Alternate Pixel Sampling (Even Pixels) RGBIN HSYNC PXCK HS ADCCK ...
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... Figure 25. Dual Channel Mode, Parallel Outputs, Alternate Pixel Sampling (Even Pixels) REV PIPE DELAY D0 D1 Figure 22. Dual Channel Mode, Parallel Outputs 5.5 PIPE DELAY PIPE DELAY D0 D2 –21– AD9884A ...
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... The fundamental idea is to have a bypass capacitor within about 0 each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9884A, as that interposes resistive vias in the path. The bypass capacitors should be connected between the power plane and the power pin ...
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... The digital inputs on the AD9884A were designed to work with 3.3 V signals. Connecting 5 V digital signals to the part may cause damage. To accommodate 5 V digital signals, we recom- mend adding a series resistor at the AD9884A pin The only exception is the two serial interface pins, SDA and SCL. On these two pins, a resistor value of 150 it should be placed between the AD9884A pin and the pull-up resistors ...
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... AD9884A 0.041 (1.03) 0.035 (0.88) 0.031 (0.78) SEATING PLANE 0.003 (0.08) MAX 0.010 (0.25) MIN OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 128-Lead Plastic Quad Flatpack (MQFP) (S-128) 0.685 (17.40) 0.677 (17.20) 0.669 (17.00) 0.134 (3.40) 0.555 (14.10) MAX 0.551 (14.00) 0.547 (13.90) 128 103 1 TOP VIEW (PINS DOWN 0.011 (0.27) 0.020 (0.50) BSC* 0.009 (0.22) ...