AD73322 Analog Devices, AD73322 Datasheet

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... This is featured on both codecs and can be used for impedance matching or scaling when interfacing to Subscriber Line Inter- face Circuits (SLICs). The AD73322 is particularly suitable for a variety of applica- tions in the speech and telephony area, including low bit rate, high quality compression, speech enhancement, recognition, and synthesis ...

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... DIGITAL GAIN TAP Gain at Maximum Setting Gain at Minimum Setting Gain Resolution Delay Settling Time 1 (AVDD = +3 V 10%; DVDD = +3 V 16.384 MHz kHz SAMP A AD73322A Min Typ Max Units Test Conditions/Comments 5VEN = 0 1.08 1.2 1. ppm/ C 0.1 F Capacitor Required from REFCAP to AGND2 130 1 ...

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... Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave 25 s Interpolator Bypassed 50 s –25 +12 +40 mV 150 150 500 pF 100 –0.1 dB –0.25 dB –0.6 dB –1.4 dB –2.8 dB –4.5 dB –7.0 dB –9.5 dB < –12.5 dB –3– AD73322 kHz SAMP kHz SAMP ...

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... AGT On 24 All Sections On 32 REFCAP On Only 0.8 REFCAP and REFOUT On Only 3.5 All Sections Off 0 All Sections Off 0.00 The above values are in mA and are typical values unless otherwise noted. AD73322A Min Typ Max DVDD – 0.8 DVDD V 0 0.8 –10 +10 10 DVDD – 0.4 DVDD V 0 0.4 – ...

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... AD73322 = 16.384 MHz kHz; DMCLK SAMP Test Conditions/Comments 5VEN = 0 5VEN = 1 0.1 F Capacitor Required from REFCAP to AGND2 5VEN = 0, Unloaded 5VEN = 1, Unloaded 5VEN = 1 Max Output Swing = (3.156/2.4) VREFCAP kHz C Gain Step Size = 0.0625 Output Unloaded Tap Gain Change of – ...

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... Single-Ended Differential 2, 8 Maximum Load Capacitance Single-Ended Differential FREQUENCY RESPONSE 9 (ADC and DAC) Typical Output Frequency (Normalized to FS) 0 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 AD73322A Min Typ Max Units +1 V – Bits 25 s 100 s 3.156 V p-p 3.17 dBm 6.312 V p-p 9.19 dBm 2 ...

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... See Table )/DMCLK. MCLK ON Comments YES REFOUT Disabled YES REFOUT Disabled YES REFOUT Disabled YES REFOUT Disabled YES REFOUT Disabled YES NO REFOUT Disabled NO YES MCLK Active Levels Equal and DVDD NO Digital Inputs Static and Equal DVDD AD73322 ...

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... AD73322 VREFCAP VREFOUT ADC Maximum Input Range Nominal Reference Level DAC Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing Single-Ended Differential Output Bias Voltage TIMING CHARACTERISTICS Limit at Parameter T = – + Clock Signals 24 24.4 3 Serial Port ...

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... D15 D14 D15 D2 Figure 4. Serial Port (SPORT) –9– AD73322 10%; AGND = DGND = MlN MAX Description See Figure 1 MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4 SCLK Period SCLK Width High SCLK Width Low ...

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... The upgrade consists of a connector that is used to connect the EZ-KIT to the AD73322 evaluation board. This option is intended for owners of the EZ-KIT Lite. 3 The EZ-KIT Lite has been modified to allow it to interface with the AD73322 evaluation board. This option is intended for users who do not already have an EZ-KIT Lite. PIN CONFIGURATIONS ...

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... Analog Input to the inverting input amplifier on Channel 2’s negative input. VFBN2 Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator. REV. B PIN FUNCTION DESCRIPTIONS –11– AD73322 ...

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... BW Bandwidth. CRx A Control Register where placeholder for an alphabetic character (A–E). There are five read/ write control registers on the AD73322—desig- nated CRA through CRE. CRx:n A bit position, where placeholder for a nu- meric character (0–7), within a control register, where placeholder for an alphabetic charac- ter (A– ...

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... Bandwidth (300 Hz–3.4 kHz –10 –25 –15 –5 5 –85 3.17 Figure 8. S/(N+D) vs. V Bandwidth (300 Hz–3.4 kHz) –13– AD73322 –75 –65 –55 –45 –35 –25 –15 –5 V – dBm0 IN (ADC @ 5 V) over Voiceband IN –75 –65 –55 –45 –35 –25 – ...

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... SINGLE-ENDED SIGMA-DELTA PGA ENABLE MODULATOR GAIN 1 DIGITAL SWITCHED 1-BIT SIGMA- TIME CAPACITOR DAC DELTA LOW-PASS LOW-PASS MODULATOR FILTER FILTER AD73322 INVERT 0/38dB SINGLE-ENDED SIGMA-DELTA PGA ENABLE MODULATOR GAIN 1 DIGITAL SWITCHED 1-BIT TIME CAPACITOR SIGMA- DAC LOW-PASS LOW-PASS DELTA FILTER FILTER ...

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... Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73322, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth (Figure 10a) ...

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... AD73322 Decimation Filter The digital filter used in the AD73322 carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bit-stream to a lower rate 16-bit word. The antialiasing decimation filter is a sinc-cubed digital filter ...

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... MUTE bit (CRD:7) in Control Register D. The output signal is dc-biased to the codec’s on-chip voltage reference. Voltage Reference The AD73322 reference, REFCAP bandgap reference that provides a low noise, temperature-compensated reference to the DAC and ADC. A buffered version of the reference is also made available on the REFOUT pin and can be used to bias other external analog circuitry ...

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... MCLK to internal DMCLK divider and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73322 features a master clock divider that allows users the flexibility of dividing externally available high frequency DSP or CPU clocks to gen- ...

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... SPORT Register Maps There are two register banks for each codec in the AD73322: the control register bank and the data register bank. The con- trol register bank consists of eight read/write registers, each eight bits wide ...

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... If the address is not zero decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the eight control registers on the AD73322. This 8-bit field holds the data that written to or read from the selected register provided the address field is zero. – ...

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... PUADC ADC Power (0 = Power-Down Power On) PUDAC DAC Power (0 = Power-Down Power On) PUREF REF Power (0 = Power-Down Power On) RU REFOUT Use (0 = Disable REFOUT Enable REFOUT) 5VEN Enable 5 V Operating Mode (0 = Disable 5 V Mode Enable 5 V Mode) –21– AD73322 ...

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... AD73322 CONTROL REGISTER D MUTE Bit CONTROL REGISTER E Bit CONTROL REGISTER F ALB/ AGTM Bit Table XVII. Control Register D Description OGS2 OGS1 OGS0 Name Description IGS0 Input Gain Select (Bit 0) ...

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... Digital Gain Tap Coefficient (Bit 10) DGTC11 Digital Gain Tap Coefficient (Bit 11) DGTC12 Digital Gain Tap Coefficient (Bit 12) DGTC13 Digital Gain Tap Coefficient (Bit 13) DGTC14 Digital Gain Tap Coefficient (Bit 14) DGTC15 Digital Gain Tap Coefficient (Bit 15) –23– AD73322 DGTC3 DGTC2 DGTC1 DGTC0 ...

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... DAC data to the device(s). As the AD73322 is a dual codec, it features two separate device addresses for programming purposes. If the AD73322 is used in a standalone configuration connected to a DSP, the two device addresses correspond to 0 and 1 ...

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... ADC will also have the MSB set to zero to indicate data word. Appendix C details the initialization and operation of an AD73322 operating in mixed mode. Note that it is not essential to load the control registers in Program Mode before setting mixed mode active ...

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... Table XXII). However, for cascade operation this field must contain a binary value that is one less than the number of de- vices in the cascade, which is 001b for a single AD73322 device configuration. –26– Word Size (16) Sampling Rate <= Serial ...

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... Figure 21. FFT (ADC 8 kHz Filtered and Decimated from 64 kHz) The AD73322 also features direct sampling at the lower rate of 8 kHz. This is achieved by the use of extended decimation regis- ters within the decimator block, which allows for the increased word growth associated with the higher effective oversampling ratio ...

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... FREQUENCY – Hz Figure 24. FFT (ADC 8 kHz Filtered and Decimated from 16 kHz) Encoder Group Delay When programmed for high sampling rates, the AD73322 offers a very low level of group delay, which is given by the following relationship: Group Delay (Decimator) = Order where: Order is the order of the decimator (= 3), ...

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... As the AD73322 can be operated at 8 kHz (see Figure 26 kHz sampling rates, which make it particularly suited for voiceband processing important to understand the action of the interpolator’s Sinc3 response. As was the case with the en- coder section, if the output signal’s frequency response is not ...

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... Figure 28. Analog Input (DC-Coupled) Analog Inputs There are several different ways in which the analog input (en- coder) section of the AD73322 can be interfaced to external circuitry. It provides optional input amplifiers which allows sources with high source impedance to drive the ADC section correctly. When the input amplifiers are enabled, the input channel is configured as a differential pair of inverting amplifiers referenced to the internal reference (REFCAP) level ...

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... If the ADC is being connected in single-ended mode, the AD73322 should be programmed for single-ended mode using the SEEN and INV bits of CRF and the inputs connected as shown in Figure 32. When operated in single-ended input mode, the AD73322 can multiplex one of the two inputs to the ADC input. 0.1 F 10k ...

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... In this circuit the AD73322 input channel is being used in single-ended mode where the internal inverting amplifier provides suitable gain to scale the input signal relative to the ADC’ ...

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... Figure 39. AD73322 Connected to TMS320C5x Cascade Operation Where it is required to configure a cascade eight codecs (4 AD73322 dual codecs necessary to ensure that the timing of the SE and RESET signals is synchronized at each device in the cascade. A simple D type flip flop is sufficient to sync each signal to the master clock MCLK Figure 40. ...

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... The analog ground plane should be allowed to run under the AD73322 to avoid noise coupling. The power supply lines to the AD73322 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals such as ...

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... The user also knows where each sample is stored. The alternative is to handle a larger number of SPORT interrupts (twice as many in the case of a single AD73322) while also having some status flags to indicate where each new sample comes from (or is destined for). ...

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... As the AD73322 is effectively a cascade of two codec units important to observe some restrictions in the sequence of send- ing initialization words to the two codecs preferable to send pairs of control words for the corresponding control registers in each codec and it is essential to send the control word for codec 2 before that for codec 1 ...

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... DAC word to the AD73322. This sequence ends at time t where the DAC register will be updated from the 16 bits 4 in the AD73322’s serial register. However, the DAC will not be updated from the DAC register until time t acceptable in certain applications. In order to reduce this delay and load the DAC at time t ...

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... Configuring an AD73322 to Operate in Data Mode This section describes the typical sequence of control words that are required to be sent to an AD73322 to set it up for data mode operation. In this sequence Registers B, C and A are programmed before the device enters data mode. This descrip- tion panel refers to Table XXIII ...

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... ADC RESULT CH1 ADC RESULT CH2 ???????????????? ???????????????? DAC WORD CH 2 ADC RESULT CH1 0111111111111111 ???????????????? DAC WORD CH 1 DAC WORD CH 2 1000000000000000 0111111111111111 –39– AD73322 DSP Rx DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH2 0000000000000000 OUTPUT CH1 0000000000000000 DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH2 1011100100001011 ...

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... DSP to use autobuffered transfers of two words). The transmit register of the DSP is loaded with the control word destined for Channel 2. This generates a transmit frame-sync (TFS) that is input to the SDIFS input of the AD73322 to indicate the start of transmission. In Step 4, Channel 1 now contains the Control Word destined for Channel 2 ...

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... DON’T CARE xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx DAC WORD CH 2 DON’T CARE 0111111111111111 xxxxxxxxxxxxxxxx DAC WORD CH 1 DAC WORD CH 2 1000000000000000 0111111111111111 –41– AD73322 DSP Rx DON’T CARE xxxxxxxxxxxxxxxx OUTPUT CH2 0000000000000000 OUTPUT CH1 0000000000000000 DON’T CARE xxxxxxxxxxxxxxxx DON’T CARE xxxxxxxxxxxxxxxx DON’ ...

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... SPORT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sample Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DAC Advance Register . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Page Topic OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Resetting the AD73322 . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 25 Digital Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPORT Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Analog Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 INTERFACING ...

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... PLANE BSC 0.0091 (0.23) 44-Lead Plastic Thin Quad Flatpack (LQFP) (ST-44A) 0.640 (16.25) SQ 0.620 (15.75) 0.063 (1.60) 0.553 (14.05) MAX SQ 0.549 (13.95 PLANE TOP VIEW (PINS DOWN) 11 MAX 12 0.042 (1.07) 0.016 (0.40) 0.057 (1.45) 0.037 (0.93) 0.012 (0.30) 0.053 (1.35) –43– AD73322 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40 0.397 (10.07) SQ 0.391 (9.93 ...