74lvc841a NXP Semiconductors, 74lvc841a Datasheet

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74lvc841a

Manufacturer Part Number
74lvc841a
Description
10-bit Transparent Latch With 5-volt Tolerant Inputs/outputs 3-state
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed
3.3 V and 5 V environment.
The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each
latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and
an output enable (pin OE) input are common to all internal latches. The 74LVC841A
consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at
the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes. When pin LE is LOW the
latches store the information that was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches
are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the pin OE input does not affect the state of the latches.
74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs;
3-state
Rev. 03 — 24 May 2004
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
Complies with JEDEC standard JESD8B/JESD36
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C.
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Product data sheet

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74lvc841a Summary of contents

Page 1

... The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and an output enable (pin OE) input are common to all internal latches. The 74LVC841A consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs enters the latches ...

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... Rev. 03 — 24 May 2004 74LVC841A Min = ...

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... Philips Semiconductors 5. Functional diagram Fig 1. Functional diagram. Fig 2. Logic symbol. 9397 750 13129 Product data sheet 10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state Fig 3. IEC Logic symbol. Rev. 03 — 24 May 2004 74LVC841A © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

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... LATCH LATCH LATCH LATCH Rev. 03 — 24 May 2004 74LVC841A LATCH LATCH LATCH LATCH LATCH LATCH ...

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... LOW) Q9 3-state latch output Q8 3-state latch output Rev. 03 — 24 May 2004 74LVC841A (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration for DHVQFN24. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

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... Function table Input Conditions V < > < Rev. 03 — 24 May 2004 74LVC841A Internal Output latches Min Max 0.5 +6 ...

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... HIGH or LOW state 3-state operating ambient in free air temperature input rise and fall times Conditions Rev. 03 — 24 May 2004 74LVC841A Min Max [1] 0 0.5 CC [1] 0.5 +6 100 65 +150 [2] - 500 Min Max 2.7 3.6 1.2 3 ...

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... 100 GND 3 5 GND 3 Rev. 03 — 24 May 2004 74LVC841A Min Typ Max [ [2] - GND 0 0 ...

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... Figure 10 and see Figure 10 and see Figure Rev. 03 — 24 May 2004 74LVC841A Min Typ Max - - 5000 Min Typ Max - 15 - 1.5 - 7.5 [2] 1.5 3.0 6 1.5 - 8.6 [2] 1.5 3.4 7 ...

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... 3 3 see Figure 10 and see Figure see Figure Rev. 03 — 24 May 2004 74LVC841A Min Typ Max - - - 2 [2] 2 [2] 1.0 0 1.0 [ ...

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... Dn input GND output < 2 and V are the typical output voltage drop that occur with the output load Rev. 03 — 24 May 2004 74LVC841A Min Typ Max - - - PHL PLH V M mna884 © ...

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... V < 2 and V are typical output voltage drop that occur with the output load The shaded areas indicate when the input is permitted to change for predicable output performance. Rev. 03 — 24 May 2004 74LVC841A t PLH V M mna885 ...

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... 0 < 2 and V are typical output voltage drop that occur with the output load Rev. 03 — 24 May 2004 74LVC841A t PZL PZH output output enabled disabled mna886 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 14

... Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z T generator. Measurement points Load 2 2 1000 . L Rev. 03 — 24 May 2004 74LVC841A V EXT D.U. mna616 of the pulse o V EXT R ...

Page 15

... 0.49 0.32 15.6 7.6 10.65 1.27 0.36 0.23 15.2 7.4 10.00 0.019 0.013 0.61 0.30 0.419 0.05 0.014 0.009 0.60 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 03 — 24 May 2004 74LVC841A detail 1.1 1.1 1.4 0.25 0.25 0.1 0.4 1.0 0.043 0.043 0.055 0.01 0.01 0.004 0.016 0.039 ...

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... V tolerant inputs/outputs; 3-state 2.5 scale (1) ( 0.38 0.20 8.4 5.4 0.65 0.25 0.09 8.0 5.2 REFERENCES JEDEC JEITA MO-150 Rev. 03 — 24 May 2004 74LVC841A detail 7.9 1.03 0.9 1.25 0.2 0.13 7.6 0.63 0.7 EUROPEAN PROJECTION © ...

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... V tolerant inputs/outputs; 3-state 2.5 scale (1) ( 0.30 0.2 7.9 4.5 0.65 0.19 0.1 7.7 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 24 May 2004 74LVC841A detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION © ...

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... 2.5 scale (1) ( 5.6 4.25 3.6 2.25 0.5 4.5 5.4 3.95 3.4 1.95 REFERENCES JEDEC JEITA - - - - - - Rev. 03 — 24 May 2004 74LVC841A detail 0.5 1.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

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... V tolerant inputs/outputs; 3-state Data sheet status Change notice Product data - = +125 C amb Product specification - Rev. 03 — 24 May 2004 74LVC841A Order number Supersedes 9397 750 13129 74LVC841A_2 9397 750 04522 74LVC841A_1 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

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... Rev. 03 — 24 May 2004 74LVC841A © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands 74LVC841A Date of release: 24 May 2004 Document order number: 9397 750 13129 ...

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