74lvc1g99dp NXP Semiconductors, 74lvc1g99dp Datasheet
74lvc1g99dp
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74lvc1g99dp Summary of contents
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Ultra-configurable multiple function gate; 3-state Rev. 01 — 3 January 2008 1. General description The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with 3-state output. The device can be configured as one of several logic functions including, ...
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... C to +125 C 74LVC1G99GT +125 C 74LVC1G99GM +125 C 4. Marking Table 2. Marking Type number 74LVC1G99DP 74LVC1G99GT 74LVC1G99GM 5. Functional diagram Fig 1. Logic symbol 74LVC1G99_1 Product data sheet Ultra-configurable multiple function gate; 3-state Description TSSOP8 plastic thin shrink small outline package; 8 leads; ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration SOT505-2 (TSSOP8) 74LVC1G99 GND 4 Transparent top view Fig 3. Pin configuration SOT833-1 (XSON8) 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2 and SOT833 GND ...
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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 74LVC1G99_1 Product data sheet Ultra-confi ...
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... NXP Semiconductors 7.1 Logic configurations Table 5. Function selection table Primary function 3-state buffer 3-state inverter 3-state 2-input multiplexer 3-state 2-input multiplexer with inverting output 3-state 2-input AND 3-state 2-input AND with one inverting input 3-state 2-input AND with two inverting inputs ...
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... NXP Semiconductors 7.3 3-state inverter functions available [1] Table 7. Function table See Figure 6. Function Input OE 3-state inverter [ HIGH voltage level LOW voltage level don’t care. Fig 6. 3-state inverter function 7.4 3-state multiplexer functions available [1] Table 8. Function table See Figure 7 ...
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... NXP Semiconductors 7.5 3-state AND/NOR functions available [1] Table 9. Function table See Figure 8. Number of inputs Function AND/NAND 2 3-state AND 2 3-state AND [ HIGH voltage level LOW voltage level. OE input 1 input 2 Fig 8. 3-state AND/NOR function [1] Table 10. Function table See Figure 9. Number of inputs Function AND/NAND ...
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... NXP Semiconductors [1] Table 11. Function table See Figure 10. Number of inputs Function AND/NAND 2 3-state AND 2 3-state AND [ HIGH voltage level LOW voltage level. OE input 1 input 2 Fig 10. 3-state AND/NOR function [1] Table 12. Function table See Figure 11. Number of inputs Function AND/NAND 2 3-state AND 2 3-state AND [ HIGH voltage level ...
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... NXP Semiconductors 7.6 3-state NAND/OR functions available [1] Table 13. Function table See Figure 12. Number of inputs Function AND/NAND 2 3-state NAND 2 3-state NAND [ HIGH voltage level LOW voltage level. OE input 1 input 2 Fig 12. 3-state NAND/OR function [1] Table 14. Function table See Figure 13. Number of inputs Function AND/NAND ...
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... NXP Semiconductors [1] Table 15. Function table See Figure 14. Number of inputs Function AND/NAND 2 3-state NAND 2 3-state NAND [ HIGH voltage level LOW voltage level. OE input 1 input 2 Fig 14. 3-state AND/NOR function [1] Table 16. Function table See Figure 15. Number of inputs Function AND/NAND 2 3-state NAND 2 3-state NAND [ HIGH voltage level ...
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... NXP Semiconductors 7.7 3-state XOR/XNOR functions available [1] Table 17. Function table See Figure 16. Function Input OE 3-state XOR [ HIGH voltage level LOW voltage level. Fig 16. 3-state XOR function [1] Table 18. Function table See Figure 17. Function Input OE 3-state XOR L [ HIGH voltage level; ...
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... NXP Semiconductors [1] Table 19. Function table See Figure 18. Function Input OE 3-state XOR L [ HIGH voltage level LOW voltage level. Fig 18. 3-state XOR function [1] Table 20. Function table See Figure 19. Function Input OE 3-state XNOR HIGH voltage level LOW voltage level. Fig 19. 3-state XNOR function ...
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... NXP Semiconductors 8. Limiting values Table 21. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors 10. Static characteristics Table 23. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I power-off leakage current ...
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... NXP Semiconductors Table 23. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I input leakage current I I OFF-state output current OZ I power-off leakage current OFF I supply current CC I additional supply current CC [1] All typical values are measured at V 11. Dynamic characteristics Table 24 ...
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... NXP Semiconductors Table 24. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions t enable time see disable time see dis power dissipation per buffer (output enabled); PD capacitance MHz; C ...
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... NXP Semiconductors 12. Waveforms input Measurement points are given in Logic levels: V and V are typical output voltage drop that occur with the output load Fig 20. The data input ( output (Y) propagation delays OE input output LOW-to-OFF OFF-to-LOW output ...
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... NXP Semiconductors Test data is given in Table 26. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 22. Load circuitry for switching times Table 26 ...
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... NXP Semiconductors Table 27. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions V negative-going see T threshold voltage Figure Figure hysteresis voltage ( Figure Figure [1] All typical values are measured at T 14. Waveforms transfer characteristics ...
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... NXP Semiconductors Fig 25. Transfer characteristic Fig 27. Typical 74LVC1G99 transfer characteristic; V 74LVC1G99_1 Product data sheet Ultra-configurable multiple function gate; 3-state mnb154 Fig 26. Definition (mA 3 Rev. 01 — 3 January 2008 74LVC1G99 V T+ ...
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... NXP Semiconductors 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC ...
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... NXP Semiconductors 16. Abbreviations Table 28. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 29. Revision history Document ID Release date 74LVC1G99_1 20080103 74LVC1G99_1 Product data sheet Ultra-confi ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 5 7.2 3-state buffer functions available . . . . . . . . . . . 5 7.3 3-state inverter functions available . . . . . . . . . . 6 7.4 3-state multiplexer functions available . . . . . . . 6 7.5 3-state AND/NOR functions available ...