74AUP1G32 Philips Semiconductors, 74AUP1G32 Datasheet
74AUP1G32
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74AUP1G32 Summary of contents
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... Low-power 2-input OR gate Rev. 01 — 2 August 2005 1. General description The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V ...
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... GND Description TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 Marking Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate Min = ...
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... GND Y 001aab640 (TSSOP5) Pin description Pin TSSOP5 XSON6 Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate mna165 Fig 2. IEC logic symbol Y mna166 n.c. GND 001aab641 Transparent top view Fig 5. Pin confi ...
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... Power-down mode output current quiescent supply current ground current storage temperature total power +125 C amb dissipation Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate Output Min Max 0.5 +4.6 - [1] 0.5 +4.6 < ...
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... 1 1 2 3 2 4 Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate Min Max 0.8 3 +125 0 200 Min Typ Max ...
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... 2 4 GND Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate Min Typ Max - - - - - - - - 0 ...
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... 3 0 GND GND. CC Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate Min Typ Max - - 0 0.30 ...
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... Figure Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate [1] Min Typ Max Unit - 16 2.4 5.1 10.9 ns 1.6 3.6 6.6 ns 1.4 3.0 5.2 ns 1.1 2.4 3.9 ns 1.0 2 ...
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... see Figure Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate [1] Min Typ Max [2] [ +125 C Min ...
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... Measurement points are given in Table Logic levels: V and V are typical output voltage drop that occur with the output load Measurement points Output Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate + +125 C Min Max Min 3.0 15.6 3.0 2.0 9.8 2.0 1.8 7.9 1 ...
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... Termination resistance should be equal to the output impedance Z T Test data Load pF and for measuring propagation delays, setup and hold times Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate EXT DUT ...
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... 1 scale (1) ( 0.30 0.25 2.25 1.35 0.65 0.15 0.08 1.85 1.15 REFERENCES JEDEC JEITA MO-203 SC-88A Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate detail 2.25 0.46 1.3 0.425 0.3 0.1 2.0 0.21 EUROPEAN PROJECTION © ...
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... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate 4 ( EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT886 ISSUE DATE 04-07-15 04-07- ...
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... Release date 74AUP1G32_1 20050802 9397 750 14678 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate Doc. number Supersedes 9397 750 14678 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 01 — 2 August 2005 74AUP1G32 Low-power 2-input OR gate © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Disclaimers Trademarks Contact information . . . . . . . . . . . . . . . . . . . . 15 74AUP1G32 Low-power 2-input OR gate © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...