EVAL6730 STMicroelectronics, EVAL6730 Datasheet - Page 8

• Manufacturer Part Number: EVAL6730
• Description: EVAL BOARD FOR L6730XX
• Manufacturer: STMicroelectronics
• Type: Motor / Motion Controllers & Driversr

Specifications of EVAL6730

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: 66W
• Voltage - Output: 3.3V
• Current - Output: 20A
• Voltage - Input: 4.5 ~ 14V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: L6730
• Input Voltage: 8 V to 52 V
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6208
• Other names: 497-5501

Pin connections and functions
3
Note:
8/52
Pin connections and functions
Figure 3.
In the L6730B the multifunction pin is: CC/OVP/UVLO.
Table 4.
Pin n.
1
2
3
SINK/OVP/UVLO
PGOOD DELAY
CC/OVP/UVLO
SYNCH
L6730B
Name
L6730
Pins connection (top view)
Pin connection
SINK/OVP/UVLO
PGOOD DELAY
PGOOD DELAY
A capacitor connected between this pin and GND introduces a delay
between the internal PGOOD comparator trigger and the external signal
rising edge. No delay can be introduced on the falling edge of the
PGOOD signal. The delay can be calculated with the following formula:
Two or more devices can be synchronized by connecting the SYNCH pins
together. The device operating with the highest F
device. The Slave devices will operate at 180° phase shift from the
Master. The best way to synchronize devices is to set their F
same value. If it is not used, the SYNCH pin can be left floating.
With this pin it is possible:
To enable-disable the sink mode current capability after SS (L6730);
To enable-disable the constant current OCP after SS (L6730B);
To enable-disable the latch mode for the OVP;
To set the UVLO threshold for the 5 V BUS and 12 V BUS.
The device captures the analog value present at this pin at the start-up
when V
TMASK
TMASK
EAREF
EAREF
SS/INH
SS/INH
SYNCH
SYNCH
COMP
COMP
GND
GND
OSC
OSC
Doc ID 11938 Rev 3
FB
FB
CC
meets the UVLO threshold.
10
10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
HTSSOP20
HTSSOP20
PGDelay
= 5 .
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
Description
0
⋅
C
( )
pF
VCC
VCC
PGOOD
PGOOD
VCCDR
VCCDR
PGND
PGND
HGATE
HGATE
PHASE
PHASE
LGATE
LGATE
BOOT
BOOT
OCL
OCL
OCH
OCH
[μs]
SW
will be the Master
L6730 - L6730B
SW
at the