R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 94
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 94 of 1222
- Download datasheet (8Mb)
Section 3 Floating-Point Unit (FPU)
An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point
value.
• When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.
• When the EN.V bit in FPSCR is 1, an invalid operation exception will generate FPU exception
If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been
input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit
in FPSCR. An exception will not be generated in this case.
The qNAN values as operation results are as follows:
• Single-precision qNaN: H'7FBF FFFF
• Double-precision qNaN: H'7FF7 FFFF FFFF FFFF
See the individual instruction descriptions for details of floating-point operations when a non-
number (NaN) is input.
3.2.3
For a denormalized number floating-point value, the exponent field is expressed as 0, and the
fraction field as a non-zero value.
In the SH2A-FPU, the DN bit in the status register FPSCR is always set to 1, therefore a
denormalized number (source operand or operation result) is always flushed to 0 in a floating-
point operation that generates a value (an operation other than copy, FNEG, or FABS).
When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is
processed as it is. See the individual instruction descriptions for details of floating-point
operations when a denormalized number is input.
Page 66 of 1190
processing. In this case, the contents of the operation destination register are unchanged.
Denormalized Numbers
N = 1: sNaN
N = 0: qNaN
31
x
30
11111111
Figure 3.3 Single-Precision NaN Bit Pattern
23
22
Nxxxxxxxxxxxxxxxxxxxxxx
R01UH0026EJ0300 Rev. 3.00
0
SH7201 Group
Sep 24, 2010
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