R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 755

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
16.6.3
1. When the DMAC writes data to SCFTDR with a TXI interrupt request, the state of the TEND
2. When one channel is used in full duplex communication with the DMAC used for transmission
3. When one channel is used in full duplex communication with the DMAC used for reception
16.6.4
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set.
Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF
receiver continues to operate.
16.6.5
The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the
serial port register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work.
During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and
SPB2DT bits should be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD
pin.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag
in such a case.
and the CPU used for reception, if the receive data are read from the receive FIFO data register
(SCFRDR) after the RDF or DR flag in the serial status register (SCFSR) has been set, the
RDF or DR flag may be cleared.
and the CPU used for transmission, if the transmit data is written to the transmit FIFO data
register (SCFTDR) after the TDFE or TEND flag in the serial status register (SCFSR) has been
set, the TDFE or TEND flags may be cleared.
Restriction on DMAC Usage
Break Detection and Processing
Sending a Break Signal
Section 16 Serial Communication Interface with FIFO (SCIF)
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