R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 736

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.4.2
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCIF are independent, so full duplex
communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be
written and read while transmitting and receiving are in progress, enabling continuous transmitting
and receiving.
Figure 16.2 shows the general format of asynchronous serial communication.
In asynchronous serial communication, the communication line is normally held in the mark
(high) state. The SCIF monitors the line and starts serial communication when the line goes to the
space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB
first), parity bit (high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit.
The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
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Serial
data
1
Operation in Asynchronous Mode
Figure 16.2 Example of Data Format in Asynchronous Communication
Start
bit
1 bit
0
(LSB)
D 0
(8-Bit Data with Parity and Two Stop Bits)
D 1
One unit of transfer data (character or frame)
D 2
Transmit/receive data
D 3
7 or 8 bits
D 4
D 5
D 6
(MSB)
D 7
Parity
bit
1 bit
or
none
0/1
R01UH0026EJ0300 Rev. 3.00
1
Stop bit
Idle state (mark state)
1 or 2 bits
1
SH7201 Group
Sep 24, 2010
1