R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 728

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9
SCFCR resets the quantity of data in the transmit and receive data FIFO registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU. It is initialized to H'0000 by a power-on reset or in deep standby mode.
Page 700 of 1190
Bit
15 to 8
7, 6
Initial value:
R/W:
Bit:
FIFO Control Register (SCFCR)
Bit Name
—
RTRG[1:0]
—
15
R
0
—
14
R
0
13
—
R
0
Initial
Value
All 0
00
12
—
R
0
11
—
R
0
R/W
R
R/W
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register (SCFSR).
The RDF flag is set to 1 when the quantity of receive
data stored in the receive FIFO register (SCFRDR) is
increased more than the set trigger number shown
below.
•
Note: In clock synchronous mode, to transfer the receive
—
R
9
0
Asynchronous mode •
00: 1
01: 4
10: 8
11: 14
data using DMAC, set the receive trigger number
to 1. If a number other than 1 is set, CPU must
read the receive data left in SCFRDR.
—
R
8
0
R/W
RTRG[1:0]
7
0
R/W
6
0
R/W
TTRG[1:0]
5
0
Clocked synchronous mode
00: 1
01: 2
10: 8
11: 14
R/W
4
0
R01UH0026EJ0300 Rev. 3.00
—
3
0
R
TFRST RFRST LOOP
R/W
2
0
SH7201 Group
R/W
Sep 24, 2010
1
0
R/W
0
0