R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 381

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
11.7
11.7.1
The 37 sources of DMA requests include the software trigger and various DMA request signal
inputs.
The DMA request source for each channel is specified by the DMA request source select bits
(DTCG) in the corresponding DMA control register A (DMCNTAn).
11.7.2
For each channel of the DMAC, a synchronous circuit is incorporated to manage DMA requests,
which are asynchronously input. As a result, a blank period of a few clock cycles appears between
activation of the DMA request and actual reflection of the request in the DMA request bits
(DREQ) of DMA control register B (DMCNTBn). Figure 11.6 shows an example of timing
between the input of a DMA request and the DMA request bit.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Figure 11.6 Example of Timing between DMA Request Input and DMA Request Bit
Edge sense setting (falling edge sense)
Level sense setting (low level sense)
[Legend]
System clock
DMA request input
DMA request bit
: Sampling point for DMA request
System clock
DMA request input
DMA request bit
DMA Requests
Sources of DMA Requests
Synchronous Circuits for DMA Request Signals
DMA request bit is on input
of the valid edge
DMA request bit is set when
the active level has been sampled
at the end of two clock periods.
DMA request bit is maintained regardless
of changes in the level of the DMA request input
Section 11 Direct Memory Access Controller (DMAC)
DMA request bit is cleared
one cycle after sampling of
the inactive level.
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