R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 336

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 11 Direct Memory Access Controller (DMAC)
11.3.3
DMCBCT is a register used to specify the number of bytes to be transferred by DMA.
The value in this register is transferred to the working byte-count register at the start of DMA
transfer, and is then decremented by the number of bytes transferred on each unit data transfer.
Decrementation is thus by the following values.
• When the transfer size is set to 8 bits (SZSEL = "000"): −1
• When the transfer size is set to 16 bits (SZSEL = "001"): −2
• When the transfer size is set to 32 bits (SZSEL = "010"): −4
When the value in the working byte count register reaches H'000 0000, DMA transfer ends (an
end due to byte count "0"). The corresponding bit of the DMA transfer end detection register
(DMEDET) is set to 1.
If the byte count reload function is disabled, the contents of the working byte count register are
returned to this register at the moment the channel for DMA transfer switches or DMA transfer
ends. If the byte count reload function is enabled, the contents of the DMA reload byte counter
register (DMRBCTn) are returned to this register.
This register must be set before transfer is initiated, regardless of whether the reload function is
enabled or disabled.
Notes: 1. Note that a setting of H'000 0000 leads to transfer of the maximum number of bytes, i.e.
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Bit
31 to 26 ⎯
25 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Current Byte Count Register (DMCBCT)
Bit Name
CBC
R/W
64 Mbytes.
31
—
15
—
R
0
R/W
30
—
14
—
R
0
R/W
29
—
13
—
R
0
Undefined R/W
Initial
Value
All 0
R/W
28
—
12
—
R
0
R/W
27
11
—
—
R
0
R/W
R
R/W
26
10
—
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of bytes to be DMA-transferred.
R/W
R/W
25
—
—
9
R/W
R/W
24
—
—
8
CBC
R/W
R/W
23
—
—
7
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
CBC
R/W
R/W
20
—
—
4
R01UH0026EJ0300 Rev. 3.00
R/W
R/W
19
—
—
3
R/W
R/W
18
—
—
2
SH7201 Group
R/W
R/W
17
Sep 24, 2010
—
—
1
R/W
R/W
16
—
—
0