R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 261
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 261 of 1222
- Download datasheet (8Mb)
SH7201 Group
"Transition to or recovery from in progress" refers to the interval from the point at which the bits
listed in table 9.5 are written to until the corresponding commands are issued.
Table 9.5
Note: Execution of a self-refresh, a transition to or recovery from power-down or deep-power-
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
2
1
0
Function
Self-refresh
Initialization sequence
Power-down
Deep-power-down
Mode register setting
down mode, an initialization sequence, or mode register setting may only be performed
when all status bits are cleared to 0. Do not rewrite the registers (bits) listed below when
any of the status bits (DSRFST, DINIST, DPWDST, DDPDST, DMRSST) is set to 1.
Bit Name
DPWDST
DDPDST
DMRSST
List of Status Registers and Bits Requiring Checking
Initial
Value
0
0
0
SDDPDCNT
Register
SDRFCNT0
SDIR1
SDPWDCNT
SDmMOD
R/W
R
R
R
Description
Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from power-down mode is in progress for a
channel from SDRAM0 to SDRAM3.
0: Initialization sequence not in progress
1: Initialization sequence in progress
Deep-Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from deep-power-down mode is in progress
for channel SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
Mode Register Setting Status
When set to 1, this bit indicates that mode register
setting is in progress for channel SDRAM0 or
SDRAM1.
0: Mode register setting not in progress
1: Mode register setting in progress
DDPDCm, DDPD
Bits
DSFENCm, DSFEN
DINIRQCm, DINIRQ
DPWDCm, DPWD
DMR
Section 9 Bus State Controller (BSC)
Page 233 of 1190
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