R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 237

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
9.4.2
CSnREC specifies the number of data recovery cycles to be inserted after read or write accesses.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 28 ⎯
27 to 24 WRCV[3:0]
23 to 20 ⎯
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6)
Bit Name
31
—
—
15
R
0
R
0
30
—
—
14
R
0
R
0
29
—
—
13
R
0
R
0
Initial
Value
All 0
0000
All 0
28
—
—
12
R
0
R
0
R/W
27
11
—
0
R
0
R/W
R
R/W
R
R/W
WRCV[3:0]
26
10
—
0
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Post-Write Data Recovery Cycle Setting
These bits specify the number of data recovery cycles
to be inserted after write accesses to the external bus.
If a value other than 0 is selected, between 1 and 15
data recovery cycles are inserted when a write access
to the external bus is followed by a read access to the
external bus. (Data recovery cycles are inserted even
when access is performed sequentially to the same
CSC channel.) Note that if idle cycles occur between
accesses to the external bus, the number of data
recovery cycles inserted is reduced by the number of
idle cycles.
0000: 0 cycle
0001: 1 cycles
1111: 15 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
—
0
R
9
0
:
R/W
24
—
0
R
8
0
23
—
—
R
0
R
7
0
22
—
—
R
0
R
6
0
21
—
—
R
0
R
5
0
Section 9 Bus State Controller (BSC)
20
—
—
R
0
R
4
0
R/W
19
—
0
R
3
0
R/W
RRCV[3:0]
18
—
0
R
2
0
Page 209 of 1190
R/W
17
—
0
R
1
0
R/W
16
—
0
R
0
0