R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 14

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.5
9.6
Section 10 Bus Monitor..................................................................................... 285
10.1
10.2
10.3
Page xiv of xxviii
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.4.11
9.4.12
9.4.13
9.4.14
9.4.15
9.4.16
9.4.17
9.4.18
Operation .......................................................................................................................... 237
9.5.1
9.5.2
Usage Note........................................................................................................................ 283
9.6.1
9.6.2
9.6.3
Register Descriptions........................................................................................................ 285
10.1.1
10.1.2
10.1.3
10.1.4
Bus Monitor Function....................................................................................................... 293
10.2.1
10.2.2
10.2.3
10.2.4
Usage Note........................................................................................................................ 298
10.3.1
SDRAMCm Control Register (SDCmCNT) (m = 0, 1).................................... 211
CSn Mode Register (CSMODn) (n = 0 to 6) .................................................... 212
CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6) ................................. 215
CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6) ................................. 217
SDRAM Refresh Control Register 0 (SDRFCNT0) ......................................... 220
SDRAM Refresh Control Register 1 (SDRFCNT1) ......................................... 221
SDRAM Initialization Register 0 (SDIR0) ....................................................... 223
SDRAM Initialization Register 1 (SDIR1) ....................................................... 225
SDRAM Power-Down Control Register (SDPWDCNT) ................................. 226
SDRAM Deep-Power-Down Control Register (SDDPWDCNT)..................... 227
SDRAMm Address Register (SDmADR) (m = 0, 1)........................................ 228
SDRAMm Timing Register (SDmTR) (m = 0, 1) ............................................ 229
SDRAMm Mode Register (SDmMOD) (m = 0, 1)........................................... 231
SDRAM Status Register (SDSTR) ................................................................... 232
SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .............. 234
AC Characteristics Switching Register (ACSWR) ........................................... 236
CSC Interface.................................................................................................... 237
SDRAM Interface ............................................................................................. 247
Note on Power-on Reset Exception Handling and Deep Standby Mode
Cancellation ...................................................................................................... 283
Write Buffer...................................................................................................... 283
Note on Transition to Software Standby Mode or Deep Standby Mode........... 283
Bus Monitor Enable Register (SYCBEEN) ...................................................... 286
Bus Monitor Status Register 1 (SYCBESTS1) ................................................. 287
Bus Monitor Status Register 2 (SYCBESTS2) ................................................. 289
Bus Error Control Register (SYCBESW) ......................................................... 292
Operation when a Bus Error is Detected........................................................... 293
Illegal Address Access Detection Function ...................................................... 294
Bus Timeout Detection Function ...................................................................... 296
Combinations of Masters and Bus Errors ......................................................... 297
Operation when the CPU is Not Notified of a Bus Error.................................. 298
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010