R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 13

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.4
7.5
Section 8 Cache..................................................................................................181
8.1
8.2
8.3
8.4
Section 9 Bus State Controller (BSC)................................................................199
9.1
9.2
9.3
9.4
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
7.3.3
7.3.4
7.3.5
7.3.6
Operation .......................................................................................................................... 173
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Usage Notes ...................................................................................................................... 180
Features............................................................................................................................. 181
8.1.1
Register Descriptions ........................................................................................................ 184
8.2.1
8.2.2
Operation .......................................................................................................................... 189
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory-Mapped Cache ................................................................................................... 194
8.4.1
8.4.2
8.4.3
8.4.4
Features............................................................................................................................. 199
Input/Output Pins.............................................................................................................. 201
Area Overview.................................................................................................................. 203
9.3.1
9.3.2
Register Descriptions ........................................................................................................ 205
9.4.1
9.4.2
Break Data Register (BDR) .............................................................................. 166
Break Data Mask Register (BDMR) ................................................................. 167
Break Bus Cycle Register (BBR)...................................................................... 168
Break Control Register (BRCR) ....................................................................... 170
Flow of the User Break Operation .................................................................... 173
Break on Instruction Fetch Cycle...................................................................... 174
Break on Data Access Cycle............................................................................. 175
Value of Saved Program Counter ..................................................................... 176
Usage Examples................................................................................................ 177
Cache Structure................................................................................................. 181
Cache Control Register 1 (CCR1) .................................................................... 184
Cache Control Register 2 (CCR2) .................................................................... 186
Searching Cache................................................................................................ 189
Read Access ...................................................................................................... 191
Prefetch Operation (Only for Operand Cache) ................................................. 191
Write Operation (Only for Operand Cache)...................................................... 191
Write-Back Buffer (Only for Operand Cache).................................................. 192
Coherency of Cache and External Memory ...................................................... 194
Address Array ................................................................................................... 194
Data Array......................................................................................................... 195
Usage Examples................................................................................................ 197
Notes ................................................................................................................. 198
Address Map ..................................................................................................... 203
Data Bus Width and Pin Function Setting for Individual Areas ....................... 204
CSn Control Register (CSnCNT) (n = 0 to 6)................................................... 207
CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ......................... 209
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