C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 217
C8051F040-TB
Manufacturer Part Number
C8051F040-TB
Description
BOARD PROTOTYPING W/C8051F040
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F040-TB
Contents
Board
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F040
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits7-0:
Bits7-0:
Note:
R/W
R/W
Bit7
Bit7
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pullup on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. The state of the weak pullup is determined by the WEAKPUD bit (XBR2.7,
see SFR Definition 17.3).
P1MDOUT.[7:0]: Port1 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
R/W
R/W
Bit6
Bit6
SFR Definition 17.9. P1MDOUT: Port1 Output Mode
SFR Definition 17.8. P1MDIN: Port1 Input Mode
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.5
R/W
R/W
Bit3
Bit3
C8051F040/1/2/3/4/5/6/7
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
R/W
Bit0
R/W
Bit0
0xAD
F
0xA5
F
Reset Value
00000000
Reset Value
11111111
217
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