R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 8

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
SuperH
I
Instruction set upward compatible
with SuperH RISC Family
• Upward compatible with SH-1 and
• Compact 16/32-bit instruction code
• Flexible addressing modes.
Integrated SH-2A CPU engine and FPU
optimized for performance, low power
and cost
• Improved performance
• Better code density
• Real-time control
• Floating Point Unit (FPU):
SH-2A CPU Architecture
• Superscalar RISC engine
• 32-bit Harvard architecture
• 5-stage RISC CPU pipeline
• Instruction/Data cache
• 2-instruction/cycle execution time
• Conditional delayed branching
• Flexible addressing modes
• On-chip multiplier unit
• Prioritized exception handling
SH-2A FPU Architecture
• Supports IEEE-754 compliant
• Independent 5-stage pipeline
• Single/double-precision operation
• 16 x 32-bit floating point registers
• Supports FMAC/FDIV/FMUL/FSQRT
SH-2 Family of devices
– 1.5x performance compared to
– 75% code-size reduction compared
– 6-cycle interrupt-response time
– 1.4 GFlops performance
supports MAC operations
data types and exceptions
support
instructions
SH-2A Family Features
SH-2 architecture
to SH-2 core
®
Family of Microcontrollers & Microprocessors
Abundant Registers
• 16 x 32-bit general-purpose
• 4 x 32-bit system registers
• 4 x 32-bit control registers
• 16 x 32-bit Floating Point Registers
• Register banks
– R0 - R15
– (MACH/L) High/Low
– (PR) Procedure register
– (PC) Program counter register
– (SR) Status register
– (GBR) Global base register
– (VBR) Vector base register
– (TBR) Jump-table base register
– FPR0 - FPR15
– Allow contents of general registers
SH-2A CPU Architecture
Multiply & Accumulate registers
R0 to R14, global register (GBR),
the multiply and accumulate registers
(MACH, MACL), the procedure
register (PR), and the interrupt
vector table address offsets (VTO) to
be banked during interrupts
IBUS
IF
IF
DF
DF
ID
ID
mm
EX
EX
EX
EX
EX
EX
E1
E1
Improved Instruction Set
• 16-bit basic instructions
• 32-bit instructions for
• Delayed branch instructions.
• Register bank instructions for
• Barrel shift instructions supporting
• Multiple register save/restore
• Instruction set based on C language
Easier to program; simplified
product development
• Multitasking instead of
• Eliminates inter-processor
• Single hardware/software
for improved efficiency
improved performance
improved interrupt latency
logical and arithmetic operations
instructions
for ease of development
multiprocessing
communication
design environment
mm
MA
NA
E2
SH-2A
CPU
WB
WB
FPU
SF
SF
DATA
6

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