R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 7

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Built in hardware
multiply-accumulate unit
• 16-bit x 16-bit + 42-bit
• 32-bit x 32-bit + 64-bit
Instruction execution
• Scalar architecture:
• Superscalar architecture
• 5-stage instruction pipeline
Memory Management Unit
for RTOS (SH-3 and beyond)
• 4-Gbyte address space,
• Single virtual mode and
• Supports multiple page sizes:
• 4-entry fully-associative TLB
• 64-entry fully-associative TLB
• Supports software-controlled
• TLB contents can be accessed
(SH-1 devices)
(SH-2, SH-3, SH-4 chips)
One instruction per clock cycle
(SH-2A/SH-4/SH-4A onwards):
Maximum of two instructions per
cycle
(7-stage in SH-4A)
256 address space identifiers
(8-bit ASIDs)
multiple virtual memory mode
1KB, 4KB, 64KB, 1MB
for instructions
for instructions and operands
replacement and random-counter
replacement algorithm
directly by address mapping
Address
Single Scalar
Superscalar
Data
of two instructions
Parallel execution
Virtual Address
VPN
Branch unit
SH-2A/SH-4/SH-4A Two-Way Superscalar Architecture
(BR)
offset
MMU
Routine
Paging
Cache
Instruction
Instruction
Instruction
Tags
127
Bypass
0
1
2
Clock
A
A
B
(EX)
Integer unit
TLB
Parallel processing
Decoder 1
Inst. 1
The SuperH Architecture
TLB Miss
Handler
Data
(MT)
Instruction queue
Instruction queue
Instruction
Instruction
Instruction
Instruction queue
Instruction queue
C
D
B
Physical Address
Load/store unit
Instruction
PPN
64 bit
(LS) (MT)
Decoder 2
···
···
C
Superscalar Operations
Inst. 2
MMU Block Diagram
offset
Instruction
8 instruction x 16 bit
page boundary:
Physical
D
RAM
Floating point unit
Execution
time = 1/2
Execution time
···
(FE)
(1KB or 4 KB):
Mass Storage
Page Tables
Swap Area
Page
offset
···