R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 40

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Appendices
I
CPG/WDT
ASERAM
XYMEM
XYCNT
CACHE
H-UDI
Appendix A-3: Architecture of SH-3, SH3-DSP, and SH-4 Series
MMU
CCN
INTC
TLB
External bus
interface
SH-3, SH3-DSP Architecture
LEGEND:
ADC:
ASERAM:
AUD:
BSC:
CACHE:
CCN:
CMT:
CPG/WDT:
CPU:
DAC:
DMAC:
DSP:
INTC:
IrDA:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC:
UDI:
XYCNT:
XYMEM:
= SH3-DSP only
Serial communicatiion interface (with IRDA)
Memory management unit
Realtime clock
Serial communication interface
(with smart card interface)
Serial communication interface (with FIFO)
Translation look-aside buffer
Timer unit
User break controller
User debugging interface
X/Y memory controller
X/Y memory
A/D converter
ASE memory
Advanced user debugger
Bus state controller
Cache memory
Cache memory controller
Compare match timer
Clock pulse generator/watchdog timer
Central processing unit
D/A converter
Direct memory access controller
Digital signal processor
Interrupt controller
I/O port
DMAC
SH-3
CMT
CPU
DSP
UBC
AUD
BSC
TMU
SCIF
RTC
IrDA
ADC
DAC
SCI
32-bit
PCI
address/
data
(PCI)DMAC
(SCIF)
INTC
PCIC
CPG
RTC
TMU
SCI
I cache
(8 kB)
LEGEND:
BSC:
CPG:
DMAC: Direct memory access controller
FPU:
INTC:
ITLB:
UTLB: Unified TLB (translation lookaside buffer)
RTC:
SCI:
SCIF:
TMU:
UBC:
PCIC:
SH-4 CPU
Bus state controller
Clock pulse generator
Floating-point unit
Interrupt controller
Instruction TLB (translation lookaside buffer)
Realtime clock
Serial communication interface
Serial communication interface with FIFO
Timer unit
User break controller
PCI bus controller
SH-4 Architecture
26-bit
SH bus
address
ITLB
External (SH) bus
= SH7751R only
Cache and
controller
Lower 32-bit data
TLB
interface
UBC
BSC
32-bit SH bus data
(64-bit for SH7751)
UTLB
O cache
FPU
(16 kB)
DMAC
38

Related parts for R0K572030S000BE