R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 12

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
SuperH
I
SuperH RISC and RISC/FPU
microprocessors have excellent
graphics-handling capabilities,
allowing consumer-level prod-
ucts
enhanced features at popular
prices. Systems built with other
processor architectures require a
separate graphics chip, which
would increase complexity and
add cost.
• Superscalar architecture
• Pair single-precision data transfer –
• Vector/matrix calculation – Data can be processed
• Geometric-operation instructions – To enable high-speed
• The SH-4 supports two 32-byte store queues (SQ) to perform
(SH-2A, SH-4, and SH-4A) –
Allows FPU operations to occur
independently from non-FPU
operations of the system. This
optimizes the performance of the
graphics calculations and minimizes
flicker and graphic stalling.
Data transfer can be performed by
pair single-precision data transfer
instructions, which enable two
single-precision (each 32-bit) data
items to be transferred for double
the transfer performance.
efficiently because four multiplication operations and
one addition operation are performed in parallel.
computation with a minimum of hardware, geometric-
operation instructions perform approximate-value computa-
tions.
high-speed burst writes to external memory. While the
contents of one SQ are being transferred to external memory,
the other SQ can be written to without a penalty cycle. This
functionality is especially useful to transfer video, graphic or
display list data to the frame buffer of the graphic processor.
SuperH has 2D and 3D
graphics capabilities
with
highly
®
Family of Microcontrollers & Microprocessors
integrated,
TOP REASONS TO SELECT SuperH
Fast Data Transfers to Frame Buffers
Using the SH-4 Store Queues
SuperH Flash Roadmap
Memory
Structure
Stack (NOR)
MONOS
Metal Oxide
Nitride Oxide
Silicon
Next-Gen
NVMs
SQ 1-32 Bytes
SQ 2-32 Bytes
80MHz
SDRAM
SH-4
(0.2- 0.18µm)
50MHz
2004
(180nm)
I
Fourth-generation embedded flash, introduced in 2002,
features single-cycle access to on-chip flash memory.
• 0.18µm process, flash size as high as 1MB
• Access as fast as 12.5ns @ 80MHz
• Up to -40°C to +125°C range
• Minimum endurance up to 10,000 erase/write cycles
100MHz
SuperH MCU flash technology leadership
80MHz
80MHz
2005
2006
(150nm)
100MHz
(150nm)
2007
OF DISPLAY
PRIMITIVES
100MHz
MRAM
(130nm)
LIST
Graphic Processor
2008
DIRECT ACCESS
(90nm)
Processor
Controller
Geometry
2009
Display
Display
133MHz
2010 2011 2012 2013
(65nm)
166MHz
(45nm)
10

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