XE8000EV108 Semtech, XE8000EV108 Datasheet
XE8000EV108
Specifications of XE8000EV108
Related parts for XE8000EV108
XE8000EV108 Summary of contents
Page 1
... Ordering Information Product Temperature range XE8806AMI000 -40° °C XE8806AMI026LF -40° °C XE8806ARI000 -40°C to 125°C XE8806ARI026LF -40°C to 125°C XE8807AMI000 -40° °C XE8807AMI026LF -40° °C Memory Package type MTP die MTP TQFP32 ROM die ROM TQFP32 MTP die MTP TQFP32 www.semtech.com ...
Page 2
... Interrupt handler 9. Event handler 10. Low power RAM 11. Port A 12. Port B 13. Port D 14. Radio Asynchronous Receiver/Transmitter (BitJockey™) 15. Universal Asynchronous Receiver/Transmitter (UART) 16. Universal Synchronous Receiver/Transmitter (USRT) 17. Counters/PWM 18. The Voltage Level Detector 19. Low power comparators 20. Dimensions © Semtech 2006 TABLE OF CONTENTS XE8806A/XE8807A www.semtech.com ...
Page 3
... General overview 1.1 Top schematic 1.2 Pin map 1.2.1 TQFP-32 1.2.2 SO-28 1.2.3 SO-24 1.2.4 Bare die XE8806A 1.2.5 Bare die XE8807A 1.3 Pin assignment © Semtech 2006 XE8806A/XE8807A 1-1 1-2 1-4 1-4 1-4 1-5 1-6 1-7 1-7 www.semtech.com ...
Page 4
... The PWM is output on Port B. The VLD (voltage level detector) detects the battery end of life with respect to a programmable threshold. The CMPD contains a 4 channel comparator intended to monitor analog or digital signals whilst having a very low power consumption. © Semtech 2006 XE8806A/XE8807A 1-2 www.semtech.com ...
Page 5
... POR RC GENERATION/ POW ER XIN XTAL MANAGEMENT XOUT VREG VREG TEST CONTROLLER TEST 8 DATA REGISTERS IRQ HANDLING EVN HANDLING PORT B PB(7:0) Figure 1-1. Block schematic of the XE8806A and XE8807A circuits. © Semtech 2006 DATA MEMORY B address PORT A U control datain PORT D L dataout ...
Page 6
... In the SO-28 package, 4 pins of Port A and Port D are connected together the user to choose between the functionality of Port A or Port D for these pins. Note: if one of the pins PD(1), PD(2), PD(5), PD(6) is used as output, the pull up of the corresponding pin of Port A should be disabled in order to have low power consumption. © Semtech 2006 PB(2) 17 PB(3) ...
Page 7
... In the SO-24 package, all pins of Port A and Port D are connected together the user to choose between the functionality of Port A or Port D. Note: if one of the pins of Port D is used as output, the pull up of the corresponding pin of Port A should be disabled in order to have low power consumption. © Semtech 2006 PA(1)/PD( ...
Page 8
... PA(5) (123,1386) PA(6) (123,1072) PD(6) (123, 835) TEST (123, 545) VSS (123, 310) VREG Figure 1-5. Die dimension and pin location of the XE8806A © Semtech 2006 XEMICS 4050µm 1-6 XE8806A/XE8807A PB(1) (3787,3078) PB(0) (3787,2714) PD(2) (3787,2354) PA(2) (3787,2082) PA(1) ...
Page 9
... Sets the pin to flash programming mode XIN/XOUT Quartz crystal connections, also used for flash memory programming PA(7:0) Parallel input port A pins PB(7:0) Parallel I/O port B pins PD(7:0) Parallel I/O port D pins © Semtech 2006 XEMICS 4050µm Table 1-1. Pin assignment 1-7 XE8806A/XE8807A PB(1) (3787,3078) PB(0) ...
Page 10
... AI: analog input AO: analog output DI: digital input DO: digital output OD: nMOS open drain output PU: pull-up resistor PD: pull-down resistor SNAP: snap-to-rail function (see peripheral description for detailed description) POWER: power supply © Semtech 2006 I/O configuration ...
Page 11
... Current consumption 2.4 Operating speed 2.4.1 Flash circuit version XE8806AM 2.4.2 Flash circuit version XE8807AM 2.4.3 ROM circuit version, regulator on 2.4.4 ROM circuit version, regulator by-passed © Semtech 2006 XE8806A/XE8807A 2-1 2-2 2-2 2-3 2-4 2-4 2-5 2-5 2-6 www.semtech.com ...
Page 12
... Number of programming cycles Table 2-4. Operating range of the Flash memory Note 1. Valid only if programmed using a programming tool that is qualified Note 2. Circuits can be programmed more than 10 times but in that case, the retention time is no longer guaranteed. © Semtech 2006 Min. Max. -0.3 6 ...
Page 13
... Software using MOVE instruction using internal CPU registers and peripheral registers. 2. Using the internal voltage regulator (see Figure 2-5). 3. With the internal regulator short circuited (i.e. by connecting VREG to VBAT, see Figure 2-7). In this case, the current consumption will increase with VBAT. © Semtech 2006 Xtal Consumption comments 200 µ ...
Page 14
... CPU frequency by a factor of 2 with respect to the clock source by executing the instruction “FREQ div2”. Take care to execute this instruction before increasing the clock speed above the figures given in Figure 2-2. © Semtech 2006 VBAT VREG 2.4 - 5.5 V ...
Page 15
... Without the voltage regulator (i.e. VREG short-circuited to VBAT higher speed can be obtained. Figure 2-5. Supply configuration for ROM circuit operation using the internal regulator. © Semtech 2006 VBAT VREG 2 ...
Page 16
... ROM circuit version, regulator by-passed Figure 2-7. Supply configuration for ROM circuit operation by-passing the internal regulator Figure 2-8. Guaranteed speed as a function of supply voltage and for two temperature ranges when VREG=VBAT. © Semtech 2006 85°C 45°C 125°C 2.5 3 3.5 4 4.5 supply voltage VBAT (V) voltage regulator ...
Page 17
... CPU CONTENTS 3.1 CPU description 3.2 CPU internal registers 3.3 CPU instruction short reference © Semtech 2006 XE8806A/XE88L7A 3-1 3-2 3-2 3-4 www.semtech.com ...
Page 18
... The program counter (PC bit register that indicates the address of the instruction that has to be executed. The stack ( used to memorise the return address when executing subroutines or interrupt routines. n Instruction memory 22bit Figure 3-1. CPU internal registers © Semtech 2006 core makes it possible to compute program counter stack CPU ...
Page 19
... For an arithmetic operation with unsigned numbers occurrence of an overflow during an addition (or equivalent occurrence of an underflow during a subtraction (or equivalent). V overflow This flag is used in shift or arithmetic operations. For arithmetic or shift operations with signed numbers overflow or underflow occurs. Table 3-3. Flag description © Semtech 2006 XE8806A/XE8807A 3-3 www.semtech.com ...
Page 20
... Cpl2c reg Cpl2c reg, eaddr Inc reg1, reg2 Inc reg Inc reg, eaddr Incc reg1, reg2 Incc reg Incc reg, eaddr Dec reg1, reg2 © Semtech 2006 eaddr Operation PC := addr[15: true then PC := addr[15: true then (n>1 PC+ addr[15:0] n (n>1 PC+ n PC+ addr[15: PC+ ...
Page 21
... Setb reg,#bit[2: Clrb reg,#bit[2: Invb reg,#bit[2: © Semtech 2006 a := reg-1; if a=hFF then else reg a := DM(eaddr)-1; if a=hFF then else reg2-(1-C); if a=hFF and C=0 then else reg-(1-C); if a=hFF and C=0 then else DM(eaddr)-(1-C); if a=hFF and C=0 then else ...
Page 22
... GT op1>op2 GE op1≥op2 LT op1<op2 LE op1≤op2 Table 3-6. Jump condition description © Semtech 2006 a[ a[ xor V; a[ full; a[ empty a := reg << a[ reg[ DM(eaddr)<<1; a[0] := DM(eaddr)[7] reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16) halts the CPU no operation DM(eaddr) and will simultaneously execute the index operation ...
Page 23
... USRT (h0048-h004F) 4.2.10 UART (h0050-h0057) 4.2.11 Counter/Timer/PWM registers (h0058-h005F) 4.2.12 RF interface (h0060-h0067) 4.2.13 Comparator registers (h0072-h0073) 4.2.14 Voltage Level Detector registers (h007E-h007F) 4.2.15 RAM (h0080-h027F) © Semtech 2006 XE8806A/XE8807A 4-1 4-2 4-2 4-3 4-3 4-4 4-4 4-4 4-4 4-5 4-5 4-6 ...
Page 24
... The access mode of the different bits (see Table 4-1 for code description) 4. The reset source and reset value of the different bits The reset source coding is given in Table 4-2. To get a full description of the reset sources, please refer to the reset block chapter. © Semtech 2006 CPU ...
Page 25
... RegSysWd h0014 r0 r0 RegSysPre0 h0015 r0 r0 RegSysRcTrim1 h001B r0 r0 RegSysRcTrim2 h001C r0 r0 Table 4-4. Reset block and clock block registers © Semtech 2006 Reg00[7:0] rw,00000000,glob Reg01[7:0] rw,00000000,glob Reg02[7:0] rw,00000000,glob Reg03[7:0] rw,00000000,glob Reg04[7:0] rw,00000000,glob Reg05[7:0] rw,00000000,glob Reg06[7:0] rw,00000000,glob Reg07[7:0] rw,0000000,glob Table 4-3 ...
Page 26
... RegPDIn h0031 RegPDDir h0032 RegPDPullup PDSnapToRail[3:0] h0033 rw,0000,pconf 4.2.6 Flash programming (h0038-003B) These four registers are used during flash programming only. Refer to the flash programming algorithm documentation for more details. © Semtech 2006 PAIn[7:0] r PADebounce[7:0] rw,00000000,pconf PAEdge[7:0] rw,00000000,glob PAPullup[7:0] rw,11111111,pconf ...
Page 27
... PAIrq[7] PAIrq[6] h0042 rc1,0,glob rc1,0,glob RegIrqEnHig h0043 RegIrqEnMid h0044 RegIrqEnLow h0045 RegIrqPriority h0046 RegIrqIrq h0047 r0 r0 The origin of the different interrupts is summarised in the table below. © Semtech 2006 128Hz PAEvn[1] CntIrqB CntIrqD rc1,0,glob rc1,0,glob rc1,0,glob rc1,0,glob EvnEn[7:0] rw,00000000,glob EvnPriority[7:0] r,11111111,glob r0 r0 ...
Page 28
... UART (h0050-h0057) Name Address 7 6 RegUartCtrl UartEcho UartEnRx h0050 rw,0,glob rw,0,glob RegUartCmd SelXtal h0051 rw,0,glob r0 RegUartTx h0052 RegUartTxSta h0053 r0 r0 RegUartRx h0054 RegUartRxSta h0055 r0 r0 © Semtech 2006 Table 4-11. Interrupt source description UsrtEnWaitCond1 UsrtWaitS0 rw,0,glob r0 r0 r,0,glob ...
Page 29
... Table 4-15. RF interface (Rfif) register description. 4.2.13 Comparator registers (h0072-h0073) Name Address 7 6 RegCmpdStat CmpdStat[3:0] h0072 rca,0000,glob RegCmpdCtrl IrqOnRising[2:0] h0073 rw,000,glob Table 4-16. Low power comparator registers © Semtech 2006 CounterA[7:0] s,00000000,glob CounterB[7:0] s,00000000,glob CounterC[7:0] s,00000000,glob CounterD[7:0] s,00000000,glob CntCCkSel[1:0] CntBCkSel[1:0] rw,00,glob rw,00,glob ...
Page 30
... Table 4-17. Voltage level detector register description 4.2.15 RAM (h0080-h027F) The 512 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables stored in the RAM should be initialised before use since they can have any value at circuit start up. © Semtech 2006 ...
Page 31
... Low Power Modes 5.1 Features ................................................................................................................................5-2 5.1.1 Overview ...............................................................................................................................5-2 5.2 Operating mode ....................................................................................................................5-2 © Semtech 2006 XE8806A/XE8807A 5-1 www.semtech.com ...
Page 32
... Note recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode because this instruction can be executed when the sleep mode is left using the resetfromportA. © Semtech 2006 XE8806A/XE8807A 5-2 ...
Page 33
... Halt instruction ACTIVE Interrupt/event normal mode Figure 5-1. XE8000 operating modes. © Semtech 2006 por padnreset por padnreset portA reset STAND-BY set bit sleep low current 5-3 XE8806A/XE8807A SLEEP very low current www ...
Page 34
... Programmable Port A input combination 6.5.4 Watchdog reset 6.5.5 BusError reset 6.6 Sleep mode 6.7 Control register description and operation 6.8 Watchdog 6.9 Start-up and watchdog specifications © Semtech 2006 XE8806A/XE8807A 6-1 6-2 6-2 6-2 6-3 6-4 6-4 6-4 6-4 6-4 6-5 ...
Page 35
... The reset block is the reset manager. It handles the different reset sources and distributes them through the system. It also controls the sleep mode of the circuit. 6.3 Register map Table 6-1 gives the different registers used by this block. © Semtech 2006 register name RegSysCtrl RegSysReset RegSysWd Table 6-1 ...
Page 36
... There are 5 reset sources: • Power On Reset (POR) • External reset from the NRESET pin • Programmable port A input combination • Programmable watchdog timer reset • Programmable BusError reset on processor access outside the allocated memory map © Semtech 2006 Rw Reset Function nresetcold ...
Page 37
... Port A (if present in the product) can generate a reset signal. See the description of the Port A for further information. 6.5.4 Watchdog reset The Watchdog will generate a reset if the watchdog is not cleared in time by the processor. See chapter 6.8 describing the watchdog for further information. © Semtech 2006 Internal reset signals nresetpconf when when nresetsleep ...
Page 38
... NRESET pin to a low state. The watchdog timer can be cleared by writing consecutively the values Hx0A and Hx03 to the RegSysWd register. The sequence must strictly be respected to clear the watchdog. © Semtech 2006 XE8806A/XE8807A EnBusError ...
Page 39
... Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. In case an external clock source is used, the watchdog timeout period will be correct in so far the contents of the RegSysRCTrim1 and RegSysRCTrim2 registers are correct (see clock block documentation for more details). © Semtech 2006 POR Min ...
Page 40
... Xtal configuration ............................................................................................................................ 7-7 7.7.2 Xtal oscillator specifications............................................................................................................. 7-7 7.8 External clock.................................................................................................................................. 7-8 7.8.1 External clock configuration ............................................................................................................ 7-8 7.8.2 External clock specification ............................................................................................................. 7-8 7.9 Clock source selection .................................................................................................................... 7-8 7.10 Prescalers ....................................................................................................................................... 7-9 7.11 32 kHz frequency selector............................................................................................................. 7-10 © Semtech 2006 XE8806A/XE8807A 7-1 www.semtech.com ...
Page 41
... EnableXtal 0 EnableRc pos. RegSysMisc 7 Output16k 0 OutputCpuCk pos. RegSysPre0 7 ClearLowPrescal © Semtech 2006 rw reset r/w 0 nresetsleep Select speed for cpuck r 0 Unused r/w 0 nresetcold Enable for external clock r/w 1 nresetcold Enable Rcbias (reduces start-up time of RC nresetsleep Xtal in start phase r 0 Unused ...
Page 42
... RcFreqFine[1] 0 RcFreqFine[0] pos. RegSysPtckmode 7 Reserved 7.4 Interrupts and events map interrupt source Default mapping in the interrupt ck128Hz ck1Hz © Semtech 2006 rw reset r 000 Unused r/w 0 nresetcold Low/high freq. range (low=0) r/w 0 nresetcold RC coarse trim bit 3 r/w 0 nresetcold RC coarse trim bit 2 r/w ...
Page 43
... Semtech 2006 Figure 7-1. Clock block structure 7-4 XE8806A/XE8807A www.semtech.com ...
Page 44
... RcFreqCoarse: for each value the frequency is multiplied by 2. Incrementing the RcFreqFine code, increases the frequency by about 1.4%. The frequency of the oscillator is therefor given by: ⋅(1+9⋅RcFreqRange)⋅(1+RcFreqCoarse)⋅(1.014 Rcmin with f the RC oscillator frequency if the registers are all 0. Rcmin © Semtech 2006 XE8806A/XE8807A RcFreqFine 7-5 www.semtech.com ...
Page 45
... Note 3: frequency shift as a function of VBAT while the regulator is short-circuited to VBAT. The tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the software or hardware DFLL (digital frequency locked loop) which uses the crystal oscillator as a reference frequency. © Semtech 2006 0001 0011 0111 ...
Page 46
... Resistance XIN-VSS Rh_xout Resistance XOUT- VSS Rh_xin_xout Resistance XIN- XOUT Cp_xin Capacitance XIN- VSS Cp_xout Capacitance XOUT- VSS Cp_xin_xout Capacitance XIN- XOUT Table 7-10. Board layout specifications. © Semtech 2006 Min Typ Max Unit 32768 Hz 8 100 kΩ 1.8 2.5 3.2 fF ...
Page 47
... NRESET or after Sleep mode. The CPU clock selection is done with the bit CpuSel in RegSysClock (0= fastest clock kHz from Xtal if EnableXtal =1 and EnExtClock = 0 else from high prescaler 32 kHz output). Switching from one clock source to another is glitch free. © Semtech 2006 Min Typ Max ...
Page 48
... EnableXtal is set. Both dividing chains are reset asynchronously by the nresetglobal signal. • Bit ColdXtal=1 indicates the Xtal is in its start phase active for 32768 Xtal cycles after setting EnableXtal. © Semtech 2006 Clock targets Cpuck CpuSel=0 ...
Page 49
... If the frequency is not set correctly, all timings derived from the low prescaler will be shifted accordingly (e.g. watchdog frequencies) and some peripherals may no longer function correctly if the deviation from 32kHz is too large (e.g. the voltage level detector). © Semtech 2006 XE8806A/XE8807A 7-10 www.semtech.com ...
Page 50
... From 1’0111’011 to 1’0111’111 From 1’1000’000 to 1’1000’001 From 1’1000’010 to 1’1000’111 1’1001’000 From 1’1001’001 to 1’1111’111 Table 7-14: Table of 32kHz high prescaler tap decoder. © Semtech 2006 XE8806A/XE8807A Selected high prescaler tap Ckrcext/2 Ckrcext Ckrcext/2 ...
Page 51
... Interrupt Handler 8.1 F ....................................................................................................................................... 8-2 EATURES 8.2 O ...................................................................................................................................... 8-2 VERVIEW 8.3 R ................................................................................................................................ 8-2 EGISTER MAP 8.4 D .................................................................................................................... 8-4 ETAILED DESCRIPTION 8.5 I NTERRUPT HANDLING SOFTWARE © Semtech 2006 ...................................................................................................... 8-5 8-1 XE8806A/XE8807A www.semtech.com ...
Page 52
... Register map pos. RegIrqHig 7 RegIrqHig[7] 6 RegIrqHig[6] 5 RegIrqHig[5] 4 RegIrqHig[4] 3 RegIrqHig[3] 2 RegIrqHig[2] 1 RegIrqHig[1] 0 RegIrqHig[0] © Semtech 2006 Register name RegIrqHig RegIrqMid RegIrqLow RegIrqEnHig RegIrqEnMid RegIrqEnLow RegIrqPriority RegIrqIrq Table 8-1: IRQ handler registers rw reset r 0 nresetglobal interrupt #23 (high priority) c1 clear interrupt #23 when 1 is written r ...
Page 53
... RegIrqEnHig 7 RegIrqEnHig[7] 6 RegIrqEnHig[6] 5 RegIrqEnHig[5] 4 RegIrqEnHig[4] 3 RegIrqEnHig[3] 2 RegIrqEnHig[2] 1 RegIrqEnHig[1] 0 RegIrqEnHig[0] © Semtech 2006 rw reset r 0 nresetglobal interrupt #15 (mid priority) c1 clear interrupt #15 when 1 is written r 0 nresetglobal interrupt #14 (mid priority) c1 clear interrupt #14 when 1 is written r 0 nresetglobal interrupt #13 (mid priority) c1 clear interrupt #13 when 1 is written ...
Page 54
... RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags are set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source. © Semtech 2006 rw reset ...
Page 55
... Interrupt handling software This chapter describes an example of the software used for the interrupt handler. This software is present by default in the software development environments. It represents only one of several possible ways of handling the interrupts. © Semtech 2006 IE1 GIE IN2 IN1 IN0 … ...
Page 56
... Irq_Pa2 jump Irq_Pa3 jump Irq_CntD jump Irq_CntB © Semtech 2006 XE8806A/XE8807A ; save pc add the offset, nb instr. before table ; propagate carry ; add the offset of the regirqpriority ; propagate carry ; put RegIrqPriority = 0x00 ; RegIrqPriority = 0x01 ; RegIrqPriority = 0x02 ...
Page 57
... End of interrupt handlers ######################################################################## © Semtech 2006 XE8806A/XE8807A ; RegIrqPriority = 0x06 ; RegIrqPriority = 0x07 ; RegIrqPriority = 0x08 ; RegIrqPriority = 0x09 ; RegIrqPriority = 0x0A ; RegIrqPriority = 0x0B ; RegIrqPriority = 0x0C ; RegIrqPriority = 0x0D ; RegIrqPriority = 0x0E ...
Page 58
... Event Handler 9.1 FEATURES ................................................................................................................................... 9-2 9.2 OVERVIEW ................................................................................................................................... 9-2 9.3 REGISTER MAP............................................................................................................................ 9-2 9.4 DETAILED DESCRIPTION............................................................................................................ 9-3 © Semtech 2006 XE8806A/XE8807A 9-1 www.semtech.com ...
Page 59
... The addresses given in Table 9-1 are the default values and may be different in some products. pos. RegEvn 7 RegEvn[7] 6 RegEvn[6] 5 RegEvn[5] 4 RegEvn[4] 3 RegEvn[3] 2 RegEvn[2] 1 RegEvn[1] 0 RegEvn[0] © Semtech 2006 Register name RegEvn RegEvnEn RegEvnPriority RegEvnEvn Table 9-1: EVN handler registers. rw reset function r 0 nresetglobal event #7 (high priority) c1 clear event #7 when written nresetglobal event #6 (high priority) c1 ...
Page 60
... The 8 event sources are divided into 2 levels of priority: High (4 event sources) and Low (4 event sources). Those 2 levels of priority are directly mapped to those supported by the CoolRisc (EV0 and EV1; see CoolRisc documentation for more information). © Semtech 2006 rw reset ...
Page 61
... IE2 RegEvn 7 7 RegEvnEn © Semtech 2006 IE1 GIE IN2 IN1 IN0 Figure 9-1. Event handler principle. 9-4 XE8806A/XE8807A EV1 EV0 www.semtech.com ...
Page 62
... Low Power RAM 10.1 Features ..............................................................................................................................10-2 10.1.1 Overview .............................................................................................................................10-2 10.2 Register map.......................................................................................................................10-2 © Semtech 2006 XE8806A/XE8807A 10-1 www.semtech.com ...
Page 63
... Reg00 7-0 Reg00 7-0 Reg01 7-0 Reg02 7-0 Reg03 7-0 Reg04 7-0 Reg05 7-0 Reg06 7-0 Reg07 © Semtech 2006 rw reset function rw 0 low-power data memory rw 0 low-power data memory rw 0 low-power data memory rw 0 low-power data memory rw 0 low-power data memory ...
Page 64
... Port A 11.1 FEATURES ..................................................................................................................................... 11-2 11.2 O ................................................................................................................................. 11-2 VERVIEW 11.3 R ........................................................................................................................... 11-3 EGISTER MAP 11.4 I NTERRUPTS AND EVENTS MAP 11 (PA) O ........................................................................................................... 11-4 ORT PERATION 11 ORT ELECTRICAL SPECIFICATION © Semtech 2006 ..................................................................................................... 11-4 ............................................................................................ 11-6 11-1 XE8806A/XE8807A www.semtech.com ...
Page 65
... PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent) 11.2 Overview PortA is a general purpose 8 bit wide digital input port, with interrupt capability. Figure 11-1 shows its structure. VBat 8 8 logic 8x debounce 8 Vss 1 0 © Semtech 2006 Port A RegPASnaptorail RegPAPullup 8 RegPADebounce RegPACtrl 0 8 RegPAIn 8 1 RegPAEdge ...
Page 66
... PADebounce[7:0] pos. RegPAEdge 7:0 PAEdge[7:0] pos. RegPAPullup 7:0 PAPullup[7:0] pos. RegPARes0 7:0 PARes0[7:0] pos. RegPARes1 7:0 PARes1[7:0] © Semtech 2006 register name RegPAIn RegPADebounce RegPAEdge RegPAPullup RegPARes0 RegPARes1 RegPACtrl RegPASnaptorail Table 11-1: PA registers rw reset description r x pad PA[7] to PA[0] input value ...
Page 67
... When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pullup and pulldown resistors are disconnected). When the corresponding bit in RegPAPullup is 1 and in RegPASnaptorail pullup resistor is connected to the input pin. Finally, when the corresponding bit in RegPAPullup is 1 and in RegPASnaptorail is 1, the snap-to-rail function is active. © Semtech 2006 rw reset description ...
Page 68
... A reset from Port A can be inhibited by placing both PARes1[x] and PARes0[x] for at least 1 pin. Setting both PARes1[x] and PARes0[ makes the reset independent of the value on the corresponding pin. Setting both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible reset by software. © Semtech 2006 PASnaptorail[x] (last) externally forced PA[x] ...
Page 69
... Port A electrical specification sym description V Input high voltage 0.7*VBAT INH V Input low voltage INL R Pull-up resistance PU Cin Input capacitance Note 1: this value is indicative only since it depends on the package. © Semtech 2006 min typ max unit Comments VBAT V VSS 0.2*VBAT kΩ 2.5 pF Table 11-13 ...
Page 70
... Port B analog configuration ...................................................................................................... 12-4 12.5.2 Port B analog function specification ......................................................................................... 12-5 12.6 Port B function capability.......................................................................................................... 12-5 12.7 Port B digital capabilities .......................................................................................................... 12-6 12.7.1 Port B digital configuration ....................................................................................................... 12-6 12.7.2 Port B digital function specification........................................................................................... 12-7 12.8 Low power comparators ........................................................................................................... 12-7 © Semtech 2006 XE8806A/XE8807A 12-1 www.semtech.com ...
Page 71
... Port multi-purpose 8 bit Input/output port. In addition to digital behavior, all pins can be used for analog signals. Each port terminal can be individually selected as digital input or output or as analog for sharing one of four possible analog lines. 12.3 Register map Table 12-1 shows the Port B registers. © Semtech 2006 register name RegPBOut RegPBIn RegPBDir ...
Page 72
... PB[4] analog PB[3] analog PB[2] analog PB[1] analog PB[0] analog © Semtech 2006 reset description in digital mode Pad PB[7-0] output value Table 12-2: RegPBOut reset description in digital mode Pad PB[7-0] input status Table 12-3: RegPBIn reset description in digital mode Pad PB[7-0] direction (0=input) ...
Page 73
... RegPBPullup,#0bXX0XX0XX analog mode (move RegPBAna,#0bXX1XX1XX) - select the analog line3 (move RegPBDir,#0bXX1XX1XX and move RegPBOut,#0bXX1XX1XX) - apply the analog line to the output (move RegPBPullup,#0bXX1XX1XX) - © Semtech 2006 PBPullup[x] PB[x] selection ...
Page 74
... PBOut(3). However, PBDir(3) must be set to 1. The frequency and duty cycle of the clock signal are given in Figure 12- the frequency of fastest clock present in the circuit. max Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value contained in PBOut(2). However, PBDir(2) must be set to 1. © Semtech 2006 min typ max unit 11 kΩ ...
Page 75
... After power-on reset, the Port B is configured as an input port with pull-up. During power-on reset (see reset block documentation) however, the pin PB[1] is pulled down in stead of pulled up. Once the power-on reset completed, the pin PB[1] is pulled up, exactly as the other Port B pins. © Semtech 2006 CpuSel f1 ...
Page 76
... CMPD in analog mode without selecting any analog lines. This to avoid high power consumption in the digital input buffer when analog or slowly varying digital signals are applied. © Semtech 2006 min typ max ...
Page 77
... Port D 13.1 Features 13.2 Overview 13.3 Register map 13.4 Port D (PD) Operation 13.5 Port D electrical specification © Semtech 2006 XE8806A/XE8807A 13-1 13-2 13-2 13-2 13-3 13-4 www.semtech.com ...
Page 78
... Figure 13-1 shows its structure. VBat logic Vss 13.3 Register map There are four registers in the Port D (PD), namely RegPDIn, RegPDOut, RegPDDir and RegPDPullup. Table 13-2 to Table 13-5 show the mapping of control bits and functionality of these registers. © Semtech 2006 Figure 13-1 : structure of PortD ...
Page 79
... Port D. In case of possible noise on input signals, a software debouncer or an external filter must be realised. Pull-up/Snap to Rail: When configured as an input (PDDir[x]=0), pull-ups are available on every pin. The pull-up function of the pins is controlled two by two by the PDPullup and PDSnapToRail bits in the register RegPDPullup. When a bit © Semtech 2006 Rw Reset Description r ...
Page 80
... INH V Input low voltage INL V Output high voltage VBAT-0 Output low voltage OL R Pull-up resistance PU Cin Input capacitance Note 1: this value is indicative only since it depends on the package. © Semtech 2006 PDSnapToRail[x] (last) externally forced PD[2x(+1)] value min typ max unit Comments ...
Page 81
... Microcontroller clock source derived from XE1202 crystal oscillator 14.12.2.3 Reception mode using NRZ coding and the XE1202 bit and message synchronizer 14.12.2.4 Reception mode using Manchester coding 14.12.2.5 Transmission mode using NRZ coding 14.12.2.6 Transmission mode using Manchester code © Semtech 2006 TM ) 14-1 XE8806A/XE8807A 14-2 14-2 14-2 14-3 ...
Page 82
... External clock Enable/Bypass Match clock Prescaler clock RFIF2 Transmission Clock RFIF3 Output Stream Figure 14-1 : PCM Encoder / Decoder Structure © Semtech 2006 PCM Encoder / Decoder Shift Register PCM Decoder PCM FIFO Ctrl Sig. Enable/Bypass Status. Clock Baudrate / PCM Type Ctrl Sig. ...
Page 83
... RfifBRCoarse(1:0) 3-0 RfifBRFine(3:0) pos. RegRfifCmd2 7-6 RfifEnStart(1:0) 5 RfifEnCod 4 RfifRxClock 3 RfifTxClock 2-0 RfifPCM(2:0) © Semtech 2006 register name RegRfifCmd1 RegRfifCmd2 RegRfifCmd3 RegRfifTx RegRfifTxSta RegRfifRx RegRfifRxSta RegRfifRxSPat Table 14-1: Rfif registers rw reset - - r/w 00 nresetglobal Select baud rate (coarse selection) r/w ...
Page 84
... RfifRxFifoFull 2 RfifRxStartDet 1 RfifRxBusy 0 RfifRxReady = RfifRxNotEmpty pos. RegRfifRxSPat 7-0 RfifRxSPat © Semtech 2006 rw reset r/w 000 nresetglobal ‘1’ enable the Rx Irq sources (see page r/c1 000 nresetglobal Rx Irq Status (see page 14-11) r/w 0 nresetpconf ‘1’ enable Rfif reception mode r/w 0 nresetpconf ‘ ...
Page 85
... Delay Modulation or Miller code: in this format one message bit is represented by two chips. This code contains clock information. The interface can receive and transmit coded or uncoded messages. The coding/decoding function is enabled/disabled using the bit RfifEnCod (1 = enable) in the register RegRfifCmd2. © Semtech 2006 interrupt source Irq_Rfif_Rx Irq_Rfif_Tx ...
Page 86
... Reception mode: detailed description The interface is configured in reception mode by setting the bit RfifEnRx (1 = enable) and clearing the bit RfifEnTx (0 = disable transmission) in the register RegRfifCmd3. The input data stream coming from the receiver has to be connected to the RFIF0 pin. © Semtech 2006 Types of PCM Codes 1 1 ...
Page 87
... The first bit in the FIFO is the first valid bit decoded after the detected start sequence. The bit RfifRxStartDet has to be cleared by software by writing the bit. © Semtech 2006 XE8806A/XE8807A 14-7 ...
Page 88
... RFIF2 (also called “match”, see Figure 14-1) indicates the first valid bit of the message. This edge has to occur during the first half of the first bit as shown in Figure 14-4. The minimal width of the pulse is half a bit. © Semtech 2006 start detection mode ...
Page 89
... This is shown in Figure 14-5 and Figure 14-6 where an identical input data bit stream and an identical pattern give the same start sequence detection independent from the decoded data. RfifRxSPat=10011111 NRZ - Level decoded data 1 0 Figure 14-5. Pattern start detection in NRZ-Level for RfifRxSPat[7:0]=10011111 © Semtech 2006 ...
Page 90
... FIFO contents. The detection of a new start sequence will also clear the RfifRxFifoOverrun bit and the FIFO contents. The first bit that is received can be found in the position RfifRx[0], the second bit in the position RfifRx[1] and so on. © Semtech 2006 first bit in FIFO start sequence 1 ...
Page 91
... The interrupt is enabled in the interrupt manager block. 14.9.3 Transmission encoding The transmission encoder can be bypassed by clearing the bit RfifEnCod in register RegRfifCmd2. The bit stream on the RFIF3 pin is then directly connected to the output of the shift register. © Semtech 2006 XE8806A/XE8807A 14-11 www.semtech.com ...
Page 92
... If required, a bit synchronization clock can be generated on the pin RFIF2 if the data is uncoded or if the NRZ coding is used (bits RfifEnCod and RfifPCM[2:0] in RegRfifCmd2). To generate this clock, the bit RfifTxClock in RegRfifCmd2 has to be set. The timing of the generated clock is shown in Figure 14-7. © Semtech 2006 Bi-Phase/Manchester Space ...
Page 93
... RfifBRCoarse and RfifBRFine. Note that the baud rate is the rate at which the chips are transmitted and is twice the bit rate in Manchester and Miller coding since these codes use two chips per bit (see chapter 14.7). © Semtech 2006 NRZ - Level Bi-Phase - Level ...
Page 94
... XE1201A can be driven by pins of a parallel port. The 3-wire configuration data bus of the XE1201A is used to set-up the circuit by writing in the registers A, B and C. The interface can be driven by a hardware SPI software SPI on a parallel port. Pins of the RF interface RFIF0 to RFIF3 that are not used may remain floating. © Semtech 2006 coarse 00 01 ...
Page 95
... The messages are sent at a data rate of 16 kbit/s. The following paragraphs will show how to set-up the XE1201A, how to set-up the RF interface and how to handle the received data. © Semtech 2006 data RFIF0 ...
Page 96
... At each new interrupt, we can now read 4 bytes of the received message by reading the register RegRfifRx 4 consecutive times. The interrupt should be served before the next byte is received since otherwise data may be © Semtech 2006 12 11 ...
Page 97
... The decoder is enabled and set to Manchester Mark decoding by setting RfifEnCod = 1 and RfifPCM = 100. The start detection by protocol violation is enabled by setting RfifEnStart = 01. The start sequence detection interrupt is enabled by setting RfifRxIrqEn = 001. The set-up of the interface is summarized in the Table 14-23. © Semtech 2006 ...
Page 98
... RfifBRFine = 0000. The external bit synchronization clock is switched off by clearing the bit RfifTxClock = 0. The encoder is enabled and set to NRZ space encoding by setting RfifEnCod = 1 and RfifPCM = 010. The set-up of the interface is summarized in the Table 14-24. © Semtech 2006 Register contents RegRfifCmd1 00000000 ...
Page 99
... RC oscillator frequency could be slightly increased to 1.04 MHz which gives fine*coarse=13. The external bit synchronization clock is switched off by clearing the bit RfifTxClock = 0. The encoder is enabled and set to Miller encoding by setting RfifEnCod = 1 and RfifPCM = 111. The set-up of the interface is summarized in Table 14-26. © Semtech 2006 ...
Page 100
... If the XE1202A is used as a receiver only, the connection RFIF3 – TXD is not required. If the bit synchronizer in the XE1202A is not used, the connection RFIF1 – CLKD is not required. If the start sequence detection is not used, the connection RFIF2 – PATTERN is not required. © Semtech 2006 XE8806A/XE8807A 14-20 ...
Page 101
... ADParam_Clkfreq[1:0] to select the frequency between 9.75MHz and 1.22MHz (see XE1202A datasheet for details). To select the external clock in the microcontroller, set the bit EnExtClk = 1 in the register RegSysClk. Be aware that the external clock is divided the input (see the clock block documentation for more details). © Semtech 2006 data RFIF0 [clock] ...
Page 102
... The decoder is enabled and set to NRZ Mark decoding by setting RfifEnCod = 1 and RfifPCM = 001. The external start pattern detection is enabled by setting RfifEnStart = 10. The start sequence detection interrupt is enabled by setting RfifRxIrqEn = 001. The set-up of the interface is summarized in the Table 14-28. © Semtech 2006 ...
Page 103
... RTParam_BW = 00. The baud rate is set to 4.8 kb/s by writing FSParam_BR = 000. The bit synchronizer is enabled (RTParam_bits = 1). The pattern recognition is disabled (ADParam_Pattern =0). Register Register Address RTParam1 RTParam2 FSParam1 FSParam2 FSParam3 DataOut ADParam1 ADParam2 © Semtech 2006 Register contents RegRfifCmd1 00000000 RegRfifCmd2 10100001 RegRfifCmd3 00100010 Table 14-28. RF interface set- ...
Page 104
... FIFO (overrun error which sets the flag RfifRxFifoOverrun) or because the start sequence of the next message is detected which resets the reception FIFO. When the complete message is received, the start sequence detection interrupt may be enabled again (RfifRxIrqEn = 001) and the sequence starts all over again. © Semtech 2006 01000 0 0 ...
Page 105
... Table 14-19). This can be done by setting RfifBRCoarse = 00 and RfifBRFine = 0000. The external bit synchronization clock is switched off by clearing the bit RfifTxClock = 0. The encoder is enabled and set to NRZ Level encoding by setting RfifEnCod = 1 and RfifPCM = 000. The set-up of the interface is summarized in the Table 14-32. © Semtech 2006 ...
Page 106
... We can approximate this at 2. This can be done by setting RfifBRCoarse = 00 and RfifBRFine = 0001. The external bit synchronization clock is switched off by clearing the bit RfifTxClock = 0. The encoder is enabled and set to Manchester Space encoding by setting RfifEnCod = 1 and RfifPCM = 010. The set-up of the interface is summarized in Table 14-34. © Semtech 2006 ...
Page 107
... FIFO to the transmission shift register. The first 4 bytes of the message can then be written to RfifTx. At each occurrence of the interrupt, 4 bytes of the message can be written to the FIFO until the end of the message is reached. The whole operation starts over again for the next message. © Semtech 2006 Register contents ...
Page 108
... UART on the RC oscillator or external clock source...................................................................... 15-3 15.7 UART on the crystal oscillator ....................................................................................................... 15-4 15.8 Function description ...................................................................................................................... 15-5 15.8.1 Configuration bits .......................................................................................................................... 15-5 15.8.2 Transmission................................................................................................................................. 15-5 15.8.3 Reception ...................................................................................................................................... 15-6 15.8.4 Interrupt or polling ......................................................................................................................... 15-7 15.9 Software hints ............................................................................................................................... 15-7 © Semtech 2006 XE8806A/XE8807A 15-1 www.semtech.com ...
Page 109
... UartEnRx r/w 5 UartEnTx r/w 4 UartXRx r/w 3 UartXTx r/w 2-0 UartBR(2:0) r/w © Semtech 2006 register name RegUartCtrl RegUartCmd RegUartTx RegUartTxSta RegUartRx RegUartRxSta Table 15-1: Uart register default addresses reset 0 nresetglobal Select input clock RC/external xtal 0 000 nresetglobal RC prescaler selection 0 nresetglobal ...
Page 110
... UART on the RC oscillator or external clock source To select the external clock or RC oscillator for the Uart, the bit SelXtal in RegUartCmd has The choice between the RC oscillator and the external clock source is made with the bit EnExtClock in RegSysClock. © Semtech 2006 reset description ...
Page 111
... In order to use the crystal oscillator as the clock source for the UART, the bit SelXtal in RegUartCmd has to be set. The crystal oscillator has to be enabled by setting the EnableXtal bit in RegSysClock. The baud rate selection is done using the UartBR bits as shown in Table 15-10. © Semtech 2006 External clock (Hz) 4’915’200 2’ ...
Page 112
... Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows that the transmitter is busy transmitting a word. A timing diagram is shown in Figure 15-1. Data is sent LSB first. New data should be written to the register RegUartTx only while UartTxBusy is 0, otherwise data will be lost. © Semtech 2006 XE8806A/XE8807A 15-5 www.semtech.com ...
Page 113
... The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the calculated parity of the received data. The bit is updated at data transfer to RegUartRx. The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected. © Semtech 2006 word 1 b0 ...
Page 114
... The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable UART transmission). 2. Write a byte to RegUartTx. 3. After an interrupt and if the message is not finished, jump End of transmission. © Semtech 2006 b6/7 parity stop Figure 15-2. UART reception timing diagram. ...
Page 115
... The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable UART reception). 2. When there is an interrupt, jump Read RegUartRxSta and check if there is no error. 4. Read data in RegUartRx data is not equal to End-Of-Line, then jump End of reception. © Semtech 2006 XE8806A/XE8807A 15-8 www.semtech.com ...
Page 116
... Universal Synchronous Receiver/Transmitter (USRT) 16.1 Features............................................................................................................................................. 16-2 16.2 Overview ............................................................................................................................................ 16-2 16.3 Register map...................................................................................................................................... 16-2 16.4 Interrupts map .................................................................................................................................... 16-4 16.5 Conditional edge detection 1.............................................................................................................. 16-4 16.6 Conditional edge detection 2.............................................................................................................. 16-4 16.7 Interrupts or polling ............................................................................................................................ 16-5 16.8 Function description ........................................................................................................................... 16-5 © Semtech 2006 XE8806A/XE8807A 16-1 www.semtech.com ...
Page 117
... It is advised to read S1 data when in receive mode from the RegUsrtBufferS1 register, which is the S1 value sampled on a rising edge of S0. 16.3 Register map Block configuration registers: pos. RegUsrtS1 rw 7-1 “0000000” UsrtS1 r/w © Semtech 2006 Register name RegUsrtS1 RegUsrtS0 RegUsrtCtrl RegUsrtCond1 RegUsrtCond2 RegUsrtBufferS1 RegUsrtEdgeS0 Table 16-1: USRT Registers reset function - ...
Page 118
... UsrtBufferS1 r pos. RegUsrtEdgeS0 rw 7-1 “0000000” UsrtEdgeS0 r © Semtech 2006 reset function - Unused 1 nresetglobal Write: clock S0 written to pad PB[4], Read: value on PB[4] (not UsrtS0 value). Table 16-3: RegUsrtS0 reset function - Unused 0 nresetglobal Clock stretching flag (0=no stretching), cleared by writing RegUsrtBufferS1 ...
Page 119
... USRT interface is enabled. Condition 2 is asserted for both modes (receiver and transmitter). The UsrtCond2 bit is read only and is cleared by all reset conditions and by writing any data to its address. Condition 2 occurrence also generates an interrupt on Irq_cond2. © Semtech 2006 default mapping in the interrupt manager RegIrqMid(7) RegIrqMid(6) ...
Page 120
... S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1 register. The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 16-4 shows the conditional clock stretching function, which is enabled by setting UsrtEnWaitCond1. © Semtech 2006 XE8806A/XE8807A 16-5 www.semtech.com ...
Page 121
... RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the RegUsrtBufferS1 register. The bit therefor indicates that a new value is present in the RegUsrtBufferS1 which was not yet read UsrtBufferS1 read Reg UsrtBufferS1 UsrtEdgeS0 © Semtech 2006 XE8806A/XE8807A Figure 16-5: S1 sampling 16-6 www.semtech.com ...
Page 122
... Block schematic .............................................................................................................................. 17-4 17.6 General counter registers operation ................................................................................................ 17-5 17.7 Clock selection ................................................................................................................................ 17-5 17.8 Counter mode selection .................................................................................................................. 17-6 17.9 Counter / Timer mode ..................................................................................................................... 17-7 17.10 PWM mode ..................................................................................................................................... 17-8 17.11 Capture function.............................................................................................................................. 17-9 17.12 Specifications ................................................................................................................................ 17-10 © Semtech 2006 XE8806A/XE8807A 17-1 www.semtech.com ...
Page 123
... When the counters C and D are not chained, they can be used either both as counters or counter C as PWM and counter D as counter. 17.3 Register map bit RegCntA 7-0 CounterA 7-0 CounterA © Semtech 2006 register name RegCntA RegCntB RegCntC RegCntD RegCntCtrlCk RegCntConfig1 RegCntConfig2 RegCntOn Table 17-1 ...
Page 124
... CascadeCD 2 CascadeAB 1 CntPWM1 0 CntPWM0 bit RegCntConfig2 rw 7-6 CapSel(1:0) rw 5-4 CapFunc(1:0) rw 3-2 Pwm1Size(1:0) rw 1-0 Pwm0Size(1:0) rw © Semtech 2006 rw reset R 00000000 nresetglobal W 00000000 nresetglobal Table 17-3. RegCntB rw reset R 00000000 nresetglobal W 00000000 nresetglobal Table 17-4. RegCntC rw reset R 00000000 nresetglobal W 00000000 nresetglobal Table 17-5. RegCntD ...
Page 125
... Counter A ckrcext PA(0) RegCntB (write) Counter B PA(1) RegCntC (write) ck1k Counter C ck32k PA(2) RegCntD (write) Counter D PA(3) © Semtech 2006 rw reset rw 0 nresetglobal Divide PA(3) frequency by 2 (1=divide nresetglobal Divide PA(2) frequency by 2 (1=divide nresetglobal Divide PA(1) frequency by 2 (1=divide nresetglobal ...
Page 126
... The CkRcExt clock is the RC oscillator or external clock. The clocks below 32kHz can be derived from the RC oscillator, the external clock source or the crystal oscillator (see the documentation of the clock block). A separate external clock source can be delivered on PortA for each individula counter. © Semtech 2006 Clock source for CounterA ...
Page 127
... The switching between different modes must be done while the concerned counters are stopped. While switching capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode change. © Semtech 2006 Counter A Counter B IrqA mode ...
Page 128
... This interrupt is additional to the interrupt which has already been generated when the counter reached the zero or the target value. © Semtech 2006 Counter C Counter D ...
Page 129
... RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values. In order to have glitch free outputs, the PWM outputs on PB(0) and PB(1) are sampled versions of these internal PWM signals, therefore delayed by one counter clock cycle. © Semtech 2006 2 1 ...
Page 130
... The capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or from the external PA(2) or PA(3) ports. Both counters use the same capture condition. © Semtech 2006 Resolution 11 ...
Page 131
... Pulse width in the low and high states for an external clock source, frequency division by 2 enabled Pulse width of external capture signals Table 17-16: Timing specifications for the counters © Semtech 2006 CapFunc Selected condition 00 Capture disabled 01 Rising edge ...
Page 132
... The Voltage Level Detector 18.1 Features.......................................................................................................................................... 18-2 18.2 Overview ......................................................................................................................................... 18-2 18.3 Register map................................................................................................................................... 18-2 18.4 Interrupt map................................................................................................................................... 18-2 18.5 VLD operation ................................................................................................................................. 18-3 © Semtech 2006 XE8806A/XE8807A 18-1 www.semtech.com ...
Page 133
... VldResult r 1 VldValid r 0 VldEn r w 18.4 Interrupt map interrupt source IrqVld © Semtech 2006 register name RegVldCtrl RegVldStat Table 18-1: Vld registers reset function 0000 reserved 0 VLD detection voltage range for VldTune = “011”: nresetglobal 2.55V 000 VLD tuning: ...
Page 134
... One can also poll the VLD and monitor the actual measurement result by reading the VldResult bit of the RegVldStat. This result is only valid as long as the VldValid bit is ‘1’. © Semtech 2006 min typ ...
Page 135
... Figure 18-1 shows the timing of the VLD. An interrupt is generated on each rising edge of VldResult. vbat Vth vld_en vld_valid vld_result Τ Τ T EOM PW PW The threshold value should not be changed during the measurement. © Semtech 2006 XE8806A/XE8807A Figure 18-1: VLD timing 18-4 www.semtech.com ...
Page 136
... Low Power Comparators 19. Low Power Comparators .............................................................................................................. 19-1 19.1 Features.......................................................................................................................................... 19-2 19.2 Overview ......................................................................................................................................... 19-2 19.3 Register map................................................................................................................................... 19-3 19.4 Interrupt map................................................................................................................................... 19-4 © Semtech 2006 XE8806A/XE8807A 19-1 www.semtech.com ...
Page 137
... Very low switching current • Per channel configurable interrupt • Hysteresis • 1 MHz operation 19.2 Overview Figure 19-1 gives an overview of this block: 4 PB[7:4] comparators (analog) enable © Semtech 2006 Cmpd 3 IrqOnRisingCh (edge selection comparator output EnIrqCh (channel enable Figure 19-1: Structure of Cmpd ...
Page 138
... Enable). Only after that may the user enable the channel interrupts with bit EnIrqCh[3:0]. 19.3 Register map There are two registers in the Cmpd, namely RegCmpdStat and RegCmpdCtrl. Table 19-3 and Table 19-4 show the mapping of the control bits and the functionality of these registers. © Semtech 2006 min typ max 500 ...
Page 139
... EnIrqCh[ Enable rw 19.4 Interrupt map interrupt source cmpd_irq © Semtech 2006 reset 0 nresetglobal 1: if the channel 3 generated an interrupt since last read of this register 0 nresetglobal 1: if the channel 2 generated an interrupt since last read of this register 0 nresetglobal 1: if the channel 1 generated an interrupt since ...
Page 140
... Physical Dimensions 20.1 SO type package 20.2 QFP type package © Semtech 2006 XE8806A/XE8807A 20-1 20-2 20-3 www.semtech.com ...
Page 141
... SO-24 0.606 0.294 0.1 (15.39 (7.47) (2.54) ) SO-28 0.705 0.294 0.1 (17.90 (7.47) (2.54) ) Table 20-1. SO package dimensions © Semtech 2006 inch inch inch inch (mm) (mm) (mm) (mm) 0.007 0.017 0.05 0.01 (0.18) (0.43) (1.27) (0.26) 0.007 0.017 ...
Page 142
... The QFP package dimensions are given in Figure 20-2 and Table 20-2 Figure 20-2. QFP type package package inch inch inch (mm) (mm) (mm) 0.276 0.276 0.039 TQFP-32 7.0 7.0 1.0 Table 20-2. Typical QFP package dimensions © Semtech 2006 inch inch inch inch (mm) (mm) (mm) (mm) 0.004 0.015 0.031 0.006 0.1 0.37 0.8 ...
Page 143
... USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise ...