AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 262
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 262 of 461
- Download datasheet (6Mb)
TWI Status Register
Register Name:
Access Type:
• TXCOMP: Transmission Completed
0 = In master, during the length of the current frame. In slave, from START received to STOP received.
1 = When both holding and shifter registers are empty and STOP condition has been sent (in Master) or received (in Slave),
or when MSEN is set (enable TWI).
• RXRDY: Receive Holding Register Ready
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in theTWI_RHR since the last read.
• TXRDY: Transmit Holding Register Ready
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
• OVRE: Overrun Error
0 = TWI_RHR has not been loaded while RXRDY was set
1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• UNRE: Underrun Error
0 = No underrun error
1 = No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP
bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
262
UNRE
31
23
15
–
–
–
7
AT91RM3400
OVRE
30
22
14
TWI_SR
Read-only
–
–
–
6
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
TXRDY
26
18
10
–
–
–
2
RXRDY
25
17
–
–
9
–
1
1790A–ATARM–11/03
TXCOMP
NACK
24
16
–
–
8
0
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