AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 250
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud
rate:
If DIV32 is 0:
If DIV32 is 1:
Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state
value. No serial transfers may occur. At reset, baud rate is disabled.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
If DIV32 is 0:
If DIV32 is 1:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, a minimum delay of four MCK cycles are inserted (or 128 MCK cycles when DIV32 is set)
between two consecutive characters.
Otherwise, the following equation determines the delay:
If DIV32 is 0:
If DIV32 is 1:
250
AT91RM3400
SPCK Baudrate
SPCK Baudrate
Delay Before SPCK
Delay Before SPCK
Delay Between Consecutive Transfers
Delay Between Consecutive Transfers
=
=
MCK
MCK
=
=
DLYBS MCK
32
2 SCBR
64
DLYBS MCK
SCBR
=
=
32
1024 DLYBCT MCK
DLYBCT MCK
1790A–ATARM–11/03
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