SI3402ISO-EVB Silicon Laboratories Inc, SI3402ISO-EVB Datasheet - Page 14

• Manufacturer Part Number: SI3402ISO-EVB
• Description: BOARD EVAL POE ISOL FOR SI3402
• Manufacturer: Silicon Laboratories Inc
• Type: PWM Controllersr

Specifications of SI3402ISO-EVB

• Main Purpose: Special Purpose DC/DC, Power Over Ethernet
• Outputs And Type: 1, Isolated
• Voltage - Output: 5V
• Voltage - Input: 44 ~ 57V
• Regulator Topology: Flyback
• Frequency - Switching: 350kHz
• Board Type: Fully Populated
• Utilized Ic / Part: Si3402
• Input Voltage: 5 V
• Output Voltage: 3.3 V
• Interface Type: Ethernet
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Product: Power Management Modules
• For Use With/related Products: Si3402
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1828

Si3402 ISO-EVB
3. General Design Checklist Items:
4. Layout Guidelines:
To help ensure first pass success, please submit your schematics and layout files to
review. Other technical questions may be sent to this e-mail address as well.
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a. ESD caps (C10–C17 in Figure 1) are strongly recommended for designs where system-level ESD
b. Never disable the soft start features. Make sure the soft start capacitor is in your schematics and
c. If your design uses an AUX supply, make sure to include a 3  surge limiting resistor in series with the
d. Silicon Labs strongly recommends the inclusion of a minimum load (250 mW) to avoid switcher pulsing
e. If using PLOSS function, make sure it’s properly terminated for connection in your PD subsystem. If
a. Make sure the VNEG pin of the Si3402 is connected to the backside of the QFN package with an
b. Keep the trace length from connecting to SWO and retuning to Vss1 and Vss2 as short as possible.
c. Usually one standard via handles 200 mA of current. If the trace will need to conduct a significant
d. Keep the circular area of the loop from the Switcher FET output to the inductor or transformer and
e. Connect the sense points to the output terminals directly to avoid load regulation issues related to IR
f.
g. If the outputs have a ground plane or positive output plane, do not connect the high current carrying
h. As a convenience in layout, please note that the IC is symmetrical with respect to CT1, CT2, SP1 and
(IEC6100-4-2) must provide >15 kV tolerance.
connected correctly.
AUX supply for hot insertion. Refer to AN296 when AUX supply is 48 V.
when no load is present, and to avoid false disconnection when less than 10 mA is drawn from the PSE.
If your load is not at least 250 mW, add a resistor load to dissipate at least 250 mW.
PLOSS is not needed, float this pin.
adequate thermal plane, as noted in the data sheet and AN296.
Make all of the power (high current) traces as short, direct, and thick as possible. It is a good practice on
a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.
amount of current from one plane to the other use multiple vias.
returning from the input filter capacitors (C1–C4) to Vss1 and Vss2 as small a diameter as possible.
Also, minimize the circular area of the loop from the output of the inductor or transformer to the Schottky
diode and retuning through the fist stage output filter capacitor back to the inductor or transformer as
small as possible. If possible, keep the direction of current flow in these two loops the same.
drops in the PSB traces. For the non-isolated case the sense points are Vposs and the sense resistor
R6. For the non-isolated case the sense points are R5 and the TLV431 pin 3.
Keep the feedback and loop stability components as far from the transformer/inductor and noisy power
traces as possible.
components and the filter capacitors through the plane. Connect them together and then connect to the
plane at a single point.
SP2. These leads can be interchanged.
vi. Carefully review the calculated values in the Summary section (cells B37 through B41):
1. Cell B37: PSE input voltage. Make sure the PSE input voltage is compatible with the PSE
2. Cell B38: PSE input power. If the power is >12.95 W (more than the IEEE 802.3af limits),
3. Cell B41: If the calculated junction temperature is >140 °C, then this cell is shaded in light
intended to power your PD.
then this cell is shaded in light RED and your PSE must be capable of sourcing the power
level shown in cell B30.
red. Consider bypassing the on-chip diodes to lower the effective junction temperature, or
reducing the output current (if possible). Other inputs in cells B9 through B13 may also need
to be adjusted to lower the calculated junction temperature.
Rev. 1.1
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