LM48557TLEVAL National Semiconductor, LM48557TLEVAL Datasheet - Page 11

no-image

LM48557TLEVAL

Manufacturer Part Number
LM48557TLEVAL
Description
BOARD EVALUATION LM48557
Manufacturer
National Semiconductor
Series
Boomer®r
Datasheet

Specifications of LM48557TLEVAL

Amplifier Type
Class AB
Output Type
1-Channel (Mono)
Voltage - Supply
2.7 V ~ 4.5 V
Operating Temperature
-40°C ~ 85°C
Board Type
Fully Populated
Utilized Ic / Part
LM48557
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Max Output Power X Channels @ Load
-
Application Information
I
The LM48557 is controlled through an I
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open drain). The LM48557 and the master can
communicate at clock rates up to 400kHz. Figure 4 shows the
I
stable during the HIGH period of SCL. The LM48557 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition (Figure
5). Each data word, device address and data, transmitted
over the bus is 8 bits long and is always followed by an ac-
knowledge pulse (Figure 6). The LM48557 device address is
11011110.
I
The I
the transition of SDA from HIGH to LOW while SCL is HIGH,
is generated, alerting all devices on the bus that a device ad-
dress is being written to the bus.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit. Set R/W = 0; the
LM48557 is a WRITE-ONLY device and will not respond to
2
2
2
C COMPATIBLE INTERFACE
C interface timing diagram. Data on the SDA line must be
C BUS FORMAT
2
C bus format is shown in Figure 6. The START signal,
2
C compatible serial
FIGURE 6. Example Write Sequence
FIGURE 5. Start and Stop Diagram
FIGURE 4. I
2
C Timing Diagram
11
R/W = 1. In other words, the LM48557 will not issue an ACK
when R/W = 1. Each address bit is latched in on the rising
edge of the clock. Each address bit must be stable while SCL
is HIGH. After the last address bit is transmitted, the master
device releases SDA, during which time, an acknowledge
clock pulse is generated by the LM48557. If the LM48557 re-
ceives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. The LM48557 has two registers, Mode Control
and Volume Control. The register address and register data
are combined into a single byte, the most significant bit (MSB)
indicates which register is being addressed. To address the
Mode Control register, set the MSB of the data byte to 0, fol-
lowed by seven bits of register data. To address the Volume
Control register, set the MSB of the data byte to 1, followed
by seven bits of register data. After the 8-bit register data word
is sent, the LM48557 sends another ACK bit. The LM48557
supports single and multi-byte write operations, any number
of data bytes can be transmitted to the device between
START and STOP conditions. Following the acknowledge-
ment of the last register data word, the master issues a STOP
bit, allowing SDA to go high while SCL is high.
300981g8
30098111
www.national.com
300981e2

Related parts for LM48557TLEVAL