ISL98003INZ-EVALZ Intersil, ISL98003INZ-EVALZ Datasheet - Page 6

• Manufacturer Part Number: ISL98003INZ-EVALZ
• Description: EVALUATION BOARD FOR ISL98003INZ
• Manufacturer: Intersil

Specifications of ISL98003INZ-EVALZ

• Main Purpose: Interface, Analog Front End (AFE)
• Embedded: No
• Utilized Ic / Part: ISL98003
• Primary Attributes: Triple 8-Bit ADC, 8x Oversampling
• Secondary Attributes: Automatic Black Level Compensation (ABLC™)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Diagrams
Data Output Setup and Hold Timing
RGB Output Data Timing and Latency
YUV Output Data Timing and Latency
PIXEL DATA
R/G/B[7:0]
DATACLK
VIDEO IN
ANALOG
DATACLK
DATACLK
DATACLK
HSYNC
VIDEO IN
ANALOG
HSYNC
G[7:0]
R[7:0]
B[7:0]
HS
HS
OUT
OUT
IN
IN
P
P
0
0
6
P
P
1
1
8 DATACLK PIPELINE LATENCY
P
8 DATACLK PIPELINE LATENCY
P
2
2
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
P
t
P
3
SETUP
3
P
WIDTH AND POLARITY
ISL98003
4
P
PROGRAMMABLE
4
t
HOLD
WIDTH AND POLARITY
P
5
PROGRAMMABLE
P
5
P
6
P
6
P
7
P
7
P
8
P
G
B
8
0
0
(U
(Y
P
O
O
D
) G
) R
9
0
P
9
0
1
(Y
(V
P
0
1
10
) G
) B
D
1
P
10
2
2
(U
(Y
P
2
2
11
)
)
D
2
P
G
R
September 12, 2008
11
2
3
(V
(Y
P
3
2
12
)
)
D
3
P
FN6760.0
12