EVAL-AD9830EBZ Analog Devices Inc, EVAL-AD9830EBZ Datasheet - Page 9

BOARD EVALUATION AD9830

EVAL-AD9830EBZ

Manufacturer Part Number
EVAL-AD9830EBZ
Description
BOARD EVALUATION AD9830
Manufacturer
Analog Devices Inc
Datasheets

Specifications of EVAL-AD9830EBZ

Main Purpose
Timing, Direct Digital Synthesis (DDS)
Utilized Ic / Part
AD9830
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
REV. A
FREQ0 REG
FREQ1 REG
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
Register
Figure 18. AD9830 Control Registers
Size
32 Bits
32 Bits
12 Bits
12 Bits
12 Bits
12 Bits
Description
Frequency Register 0. This defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
Figure 17. f
Word = 547AE148
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
RBW 1kHz
MCLK
= 50 MHz, f
VBW 3kHz
–9–
OUT
A2
0
0
0
0
1
1
1
1
D15 D14 D13 D12 D11
X
X = Don't Care
D15
MSB
= 16.5 MHz, Frequency
X
Figure 19. Addressing the Control Registers
X
A1
0
0
1
1
0
0
1
1
Figure 20. Frequency Register Bits
ST 50 SEC
STOP 25MHz
Figure 21. Phase Register Bits
X
MSB
A0
0
1
0
1
0
1
0
1
Destination Register
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
AD9830
D0
LSB
D0
LSB

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