EVL6563S-100W STMicroelectronics, EVL6563S-100W Datasheet - Page 25

• Manufacturer Part Number: EVL6563S-100W
• Description: EVAL BOARD FOR L6563(100W)
• Manufacturer: STMicroelectronics
• Type: Power Factor Correctionr

Specifications of EVL6563S-100W

• Main Purpose: Power Management, Power Factor Correction
• Embedded: No
• Utilized Ic / Part: L6563
• Primary Attributes: 100W Power Factor Correction and Preregulator Combination
• Secondary Attributes: Transition Mode & Active Tracking Boost Function.
• Board Size: 90 mm x 83 mm
• Maximum Operating Temperature: + 60 C
• Operating Supply Voltage: 90 V to 265 V
• Product: Power Management Modules
• Dimensions: 90 mm x 83 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6563S
• Other names: 497-10490

AN3065
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Layout hints
The layout of any converter is a very important phase in the design process needing
attention by the design engineers like any other design phase. Even if it the layout phase
sometimes looks time-consuming, a good layout does indeed save time during the
functional debugging and the qualification phases. Additionally, a power supply circuit with a
correct layout needs smaller EMI filters or less filter stages which allows consistent cost
saving.
Converters using the L6563S do not require any special or specific layout rule, just the
general layout rules for any power converter have to be applied carefully. Basic rules are
listed here below. They can be used for other PFC circuits having any power level, working
either in transition mode or with a fixed-off time control.
1.
2.
3.
4.
5.
6.
7.
Keep power and signal RTN separated. Connect the return pins of components
carrying high current such as the input filter, sense resistors, or the output capacitor as
close as possible. This point is the RTN star point. A downstream converter will have to
be connected to this return point.
Minimize the length of the traces relevant to the boost inductor, MOSFET drain, boost
rectifier and output capacitor.
Keep signal components as close as possible to each L6563S relevant pin. Specifically,
keep the tracks relevant to the pin #1 (INV) net as short as possible. Components and
traces relevant to the error amplifier have to be placed far from traces and connections
carrying signals with high dV/dt like the MOSFET drain. For high-power converters or
very compact PCB layouts, a 10 nF capacitor connected to pin #8 (PWM_LATCH) and
pin #12 (GND) might be required to decrease the noise picked up by this pin while it is
in its high impedance status.
Please connect heatsinks to power GND.
Add an external shield to the boost inductor and connect it to power GND.
Please connect the RTN of signal components including the feedback, PFC_OK and
MULT dividers close to the L6563S pin #14 (GND).
Connect a ceramic capacitor (100÷470 nF) to pin #14 (Vcc) and pin #12 (GND), close
to the L6563S. Connect this point to the RTN star point (see rule 1).
Doc ID 16279 Rev 2
Layout hints
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