OM6290 NXP Semiconductors, OM6290 Datasheet - Page 35
![DEMO BOARD LCD GRAPHIC DRIVER](/photos/9/4/90479/om6290_sml.jpg)
OM6290
Manufacturer Part Number
OM6290
Description
DEMO BOARD LCD GRAPHIC DRIVER
Manufacturer
NXP Semiconductors
Datasheets
1.PCF8576T1118.pdf
(44 pages)
2.OM6290.pdf
(30 pages)
3.OM6290.pdf
(51 pages)
4.OM6290.pdf
(83 pages)
Specifications of OM6290
Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16/32-Bit
Utilized Ic / Part
PCF2119, PCF8531, PCF8576
Primary Attributes
Character, Graphic and Segment LCD Drivers
Secondary Attributes
JTAG, I²C, UART & USB Interfaces
Description/function
Demo Board
Interface Type
USB, I2C, JTAG, UART
Data Bus Width
4 bit, 8 bit, 16 bit
Operating Voltage
1.8 V to 5.5 V
For Use With/related Products
PCF8576DT, PCF2119S, PCF8531
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4703
NXP Semiconductors
PCF2119X
Product data sheet
10.2.2.6 Set_CGRAM
10.2.2.7 Set_DDRAM
Bits SC and RL: Curs_disp_shift moves the cursor position or the display to the right or
left without writing or reading display data. This function is used to correct a character or
move the cursor through the display.
In 2-line displays, the cursor moves to the next line when it passes the last position (40) of
the line. When the displayed data is shifted repeatedly all lines shift at the same time;
displayed characters do not shift into the next line.
The address counter content does not change if the only action performed is shift display
(SC = 1) but increments or decrements with the shift cursor (SC = 0).
Table 21.
Set_CGRAM: Sets the CGRAM address bits ACG[5:0] into the address counter. Data can
then be written to or read from the CGRAM.
Remark: The CGRAM address uses the same address register as the DDRAM address.
This register consists of 7 bits. But with the Set_CGRAM command, only bit 5 to bit 0 are
set. Bit 6 can be set using the Set_DDRAM command first, or by using the auto-increment
feature during CGRAM write. All bits 6 to 0 can be read using the BF_AC instruction.
When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set
(e.g. by an earlier DDRAM write).
Table 22.
Set_DDRAM: Sets the DDRAM address bits ADD[6:0] into the address counter. Data can
then be written to or read from the DDRAM.
Bit
RS
R/W
7 to 6
5 to 0
Bit
RS
R/W
7
6 to 0
Symbol
-
-
-
ACG
Symbol
-
-
-
ADD
Set_CGRAM bit description
Set_DDRAM bit description
All information provided in this document is subject to legal disclaimers.
Value
0
0
01
000000 to
111111
Value
0
0
1
0000000 to
1111111
Rev. 9 — 14 April 2011
Description
see
fixed value
set CGRAM address
Description
see
fixed value
set DDRAM address
Table 10
Table 10
LCD controllers/drivers
PCF2119x
© NXP B.V. 2011. All rights reserved.
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