OM6290 NXP Semiconductors, OM6290 Datasheet - Page 35
![DEMO BOARD LCD GRAPHIC DRIVER](/photos/9/4/90479/om6290_sml.jpg)
OM6290
Manufacturer Part Number
OM6290
Description
DEMO BOARD LCD GRAPHIC DRIVER
Manufacturer
NXP Semiconductors
Datasheets
1.PCF8576T1118.pdf
(44 pages)
2.OM6290.pdf
(30 pages)
3.OM6290.pdf
(51 pages)
4.OM6290.pdf
(83 pages)
Specifications of OM6290
Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16/32-Bit
Utilized Ic / Part
PCF2119, PCF8531, PCF8576
Primary Attributes
Character, Graphic and Segment LCD Drivers
Secondary Attributes
JTAG, I²C, UART & USB Interfaces
Description/function
Demo Board
Interface Type
USB, I2C, JTAG, UART
Data Bus Width
4 bit, 8 bit, 16 bit
Operating Voltage
1.8 V to 5.5 V
For Use With/related Products
PCF8576DT, PCF2119S, PCF8531
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4703
NXP Semiconductors
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
14. Dynamic characteristics
Table 16.
V
T
[1]
[2]
[3]
[4]
PCF8531
Product data sheet
Symbol
f
f
f
t
t
Serial bus interface (see
f
t
t
t
t
t
t
C
t
t
t
t
t
fr(LCD)
osc
clk(ext)
w(RESL)
su(RESL)
SCL
LOW
HIGH
SU;DAT
HD;DAT
r
f
SU;STA
HD;STA
SU;STO
SP
BUF
amb
DD1
b
As the programming range for the internally generated V
while setting the VOP register and selecting the temperature compensation, that the V
under all conditions and including all tolerances.
LCD outputs are open circuit, inputs at V
V
V
V
Resets all logic when V
I
V
f
A reset is generated if t
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
input voltage swing of V
C
load
fr
=
= 1.8 V (1.9 V) to 5.5 V; V
DD1
DD1
DD1
LCD
b
= f
−
= total capacitance of one bus line in pF.
≤ 50 μA; outputs are tested one at a time.
40
clk(ext)
to V
to V
to V
≤ 7.7 V.
°
Dynamic characteristics
C to +85
DD3
DD3
DD3
Parameter
LCD frame frequency
oscillator frequency
external clock frequency
RES LOW pulse width
RES LOW set-up time
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
data set-up time
data hold time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
set-up time for a repeated START condition
hold time (repeated) START condition
set-up time for STOP condition
pulse width of spikes that must be
suppressed by the input filter
bus free time between a STOP and START
condition
/480 or f
= 2.75 V; V
= 2.85 V; V
= 2.75 V; V
osc
°
C; unless otherwise specified.
/480.
w(RESL)
DD1
SS
LCD
LCD
LCD
Figure
to V
< V
= 3.5 V; f
= 7.0 V; voltage multiplier = 3 × V
= 9.0 V; f
DD2
POR
> 3 ns (see
DD
.
22)
.
and V
[3]
osc
osc
DD
= 34 kHz.
= 34 kHz.
DD3
Figure
All information provided in this document is subject to legal disclaimers.
or V
= 2.5 V to 4.5 V; V
SS
21).
; bus inactive.
Rev. 05 — 10 August 2010
LCD
allows values above the maximum allowed V
Conditions
V
on bus
DD
DD
; f
= 3.0 V
osc
SS1
= 34 kHz.
= V
SS2
= 0 V; V
[1]
[2]
[4]
[4]
Min
40
20
20
300
-
0
1.3
0.6
100
0
20 + 0.1C
20 + 0.1C
-
0.6
0.6
0.6
-
1.3
LCD
DD1
maximum limit of 9 V will never be exceeded
to V
b
b
DD3
Typ
66
34
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
34 x 128 pixel matrix driver
≤
V
LCD
LCD
, the user must ensure,
≤
PCF8531
Max
135
65
65
-
30
400
-
-
-
0.9
0.3
0.3
400
-
-
-
50
-
© NXP B.V. 2010. All rights reserved.
9.0 V;
IL
and V
IH
Unit
Hz
kHz
kHz
ns
μs
kHz
μs
μs
ns
ns
μs
μs
pF
μs
μs
μs
ns
μs
, with an
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