W7CF128M1XA-H20PC-001.01 Wintec Industries, W7CF128M1XA-H20PC-001.01 Datasheet - Page 44

IC MEMORY

W7CF128M1XA-H20PC-001.01

Manufacturer Part Number
W7CF128M1XA-H20PC-001.01
Description
IC MEMORY
Manufacturer
Wintec Industries

Specifications of W7CF128M1XA-H20PC-001.01

Memory Size
128M bytes
Memory Type
CompactFLASH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
385-1037
WintecCF-W7CF-H_v2.2 ROHS
June 2006  Wintec Industries, Inc.
INDUSTRIAL GRADE CompactFlash
W7CFxxxA-H Series ROHS 6/6 Compliant
32MB – 8-GB
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
ALL WAVEFORMS IN HIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
Notes:
(1) Device address consists of –CS0, -CS1, and A[02::00]
(2) Data consists of D[15::00] (16-bit) or D[07::00] (8-bit)
(3) –IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
(4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether
(4-1) Device never negates IORDY: No wait is generated.
(4-2) Device starts to drive IORDY low before tA, but causes IORDY to be asserted before tA: No wait
(4-3) Device drives IORDY low before tA: wait generated. The cycle completes after IORDY is
the cycle is to be extended is made by the host after tA from the assertion of –IORD or –IOWR. The
assertion and negation of IORDY is described in the following three cases:
generated.
reasserted. For cycles where a wait is generated and –IORD is asserted, the device shall place read
data on D15-D00 for tRD before causing IORDY to be asserted.
Figure 20: True IDE Mode I/O Timing Diagram
TM
Disk
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