W7CF128M1XA-H20PC-001.01 Wintec Industries, W7CF128M1XA-H20PC-001.01 Datasheet - Page 43

• Manufacturer Part Number: W7CF128M1XA-H20PC-001.01
• Description: IC MEMORY
• Manufacturer: Wintec Industries

Specifications of W7CF128M1XA-H20PC-001.01

• Memory Size: 128M bytes
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 385-1037

WintecCF-W7CF-H_v2.2 ROHS
June 2006  Wintec Industries, Inc.
INDUSTRIAL GRADE CompactFlash
W7CFxxxA-H Series ROHS 6/6 Compliant
32MB – 8-GB
The timing diagram for True IDE mode of operation in this section is drawn using the conventions in the ATA-4
specification, which are different than the conventions used in the PCMCIA specification. Signals are shown with
their asserted state as high regardless of whether the signal is actually negative or positive true. Consequently, the –
IORD, the –IOWR, and the –IOCS16 signals are shown in the diagram inverted from their electrical states on the
bus.
Table 43: True IDE Mode I/O Read/Write Timing
Notes: The maximum load on –IOCS16 is 1 LSTTL with a 50 pF total load. All times are in nanoseconds.
t0
t1
t2
t2
t2i
t3
t4
t5
t6
t6Z
t7
t8
t9
tRD
tA
tB
tC
Cycle time (min)
Address Valid to -IORD/-IOWR setup (min)
-IORD/-IOWR (min)
-IORD/-IOWR (min) Register (8 bit)
-IORD/-IOWR recovery time (min)
-IOWR data setup (min)
-IOWR data hold (min)
-IORD data setup (min)
-IORD data hold (min)
-IORD data tristate (max)
Address valid to –IOCS16 assertion (max)
Address valid to –IOCS16 released (max)
-IORD/-IOWR to address valid hold
Read Data Valid to IORDY active (min), if
IORDY initially low after tA
IORDY Setup time
IORDY Pulse Width (max)
IORDY assertion to release (max)
Minimum time from –IORDY high to –IORD high is 0 nsec, but minimum –IORD width shall still be met.
1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum
2) This parameter specifies the time from the negation edge of –IORD to the time that the data bus is no
3) The delay from the activation of –IORD or –IOWR until the state of IORDY is first sampled. If
4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t2,
and t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i.
This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or
greater than the value reported in the device’s identify drive data. A CompactFlash Card
implementation shall support any legal host implementation.
longer driven by the CompactFlash Card (tri-state).
IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be
completed. If the CompactFlash Card is not driving IORDY negated at tA after the activation of –
IORD or –IOWR, then t5 shall be met and tRD is not applicable. If the CompactFlash Card is driving
IORDY negated at the time tA after the activation of –IORD or –IOWR, then tRD shall be met and t5
is not applicable.
Item
TM
Disk
Mode 0
1250
(ns)
600
165
290
70
60
30
50
50
30
90
60
20
35
0
5
-
Mode 1
1250
(ns)
383
125
290
50
45
20
35
30
50
45
15
35
5
0
5
-
Mode 2
1250
(ns)
240
100
290
30
30
15
20
30
40
30
10
35
5
0
5
-
Mode 3
1250
(ns)
180
n/a
n/a
30
80
80
70
30
10
20
30
10
35
5
0
5
Mode 4
1250
(ns)
120
n/a
n/a
25
70
70
25
20
10
20
30
10
35
5
0
5
Note
1
1
1
1
2
4
4
3
41