W7CF128M1XA-H20PC-001.01 Wintec Industries, W7CF128M1XA-H20PC-001.01 Datasheet - Page 19

• Manufacturer Part Number: W7CF128M1XA-H20PC-001.01
• Description: IC MEMORY
• Manufacturer: Wintec Industries

Specifications of W7CF128M1XA-H20PC-001.01

• Memory Size: 128M bytes
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 385-1037

WintecCF-W7CF-H_v2.2 ROHS
June 2006  Wintec Industries, Inc.
INDUSTRIAL GRADE CompactFlash
W7CFxxxA-H Series ROHS 6/6 Compliant
32MB – 8-GB
2.3.2 Configuration and Status Register (Address 202H)
This register is used for observing the card state.
NOTE:
Table 19: Configuration and Status Register Function
2.3.3 Pin Replacement Register (Address 204H)
This register is used for providing the signal state of –IREQ signal when the card configured I/O card interface.
NOTE:
Table 20: Pin Replacement Register Function
CHGED (HOST->)
SIGCHG (HOST->)
IOIS8 (HOST->)
PWD (HOST->)
INTR (HOST->)
CRDY/-BSY (HOST->)
RRDY/-BSY (HOST->)
CHGED
1. 1nitial value: 00H
1. Initial value 0CH
bit 7
bit 7
0
Name
Name
SIGCHG
bit 6
bit 6
0
CRDY/-BSY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
IOIS8
bit 5
bit 5
This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to “1”.
When CHGED bit is set to “1”, -STSCHG pin is held “L” at the condition of
SIGCHG bit set to “1” and the card configured for the I/O interface.
This bit is set or reset by the host for enabling and disabling the status-change signal
(-STSCHG pin). When the card is configured I/O card interface and this bit is set to
“1”, -STSCHG pin is controlled by CHGED bit. If this bit is set to “0”, -STSCHG
pin is kept “H”.
The host sets this field to “1” when it can provide I/O cycles only with one 8-bit
data bus (D7 to D0).
When this bit is set to “1”, the card enters sleep stat (Power Down mode). When
this bit is reset to “0”, the card transfers to idle state (active mode). RRDY/-BSY bit
on Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-
BSY will not become Ready until the power state requested has been entered. This
card automatically powers down when it is idle, and powers back up when it
receives a command.
This bit indicates the internal state of the interrupt request. This bit state is available
whether I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the –IEN bit in the Device Control Register, this bit is a zero.
This bit is set to “1” when the RRDY/-BSY bit changes state. This bit may also be
written by the host
When read, this bit indicates +READY pin states. When written, this bit is used for
CRDY/-BSY bit masking
TM
Disk
bit 4
bit 4
0
0
bit 3
bit 3
0
1
Function
Function
PWD
bit 2
bit 2
1
RRDY/-BSY
INTR
bit 1
bit 1
bit 0
bit 0
0
0
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