A4490EES-T Allegro Microsystems Inc, A4490EES-T Datasheet
A4490EES-T
Specifications of A4490EES-T
A4490SES-T
Related parts for A4490EES-T
A4490EES-T Summary of contents
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Triple Output Step-Down Switching Regulator Features and Benefits ▪ Three buck converters ▪ 4 input voltage range ▪ 550 kHz fixed frequency ▪ Multiphase switching ▪ Independent control of each converter ▪ Power-on-reset flag ▪ Internal compensation ...
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... The A4490 is provided in a 20-contact × 4 mm, 0.75 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number A4490EES-T 92 pieces per tube A4490EESTR-T 1500 pieces per 7-in. reel Absolute Maximum Ratings (reference to GND) Characteristic ...
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A4490 VDD C1 100 100 kΩ ENB1 ENB2 V DD PORZ CPOR C14 470 nF ENB3 PGND Note: All capacitors ceramic X5R. Triple Output Step-Down Switching Regulator Functional Block Diagram Regulator Charge ...
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A4490 Terminal List Number Name GND 4 5 ENB2 6 7 VBB2 8 CPOR 9 PORZ PGND 14 15 ENB3 16 17 VBB3 18 VBB1 19 20 ENB1 – PAD 1 GND and ...
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A4490 1,2 ELECTRICAL CHARACTERISTICS Characteristics General VBB Quiescent Current VDD Supply Range VDD Quiescent Current REG1, REG2, and REG3 Feedback Input Bias Current Feedback Voltage 3 Output Voltage Regulation PWM Frequency Maximum Duty Cycle Minimum Duty Cycle Buck Switch On-Resistance ...
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A4490 1,2 ELECTRICAL CHARACTERISTICS Characteristics Power-On Reset Duration Protection VREGx Undervoltage Lockout Startup VREGx Undervoltage Lockout Shutdown VREGx Undervoltage Lockout Startup Hysteresis VBB Undervoltage Lockout Startup VBB Undervoltage Lockout Shutdown VBB Undervoltage Lockout Shutdown Hysteresis VBB Undervoltage Warning Threshold Junction ...
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A4490 Basic Operation The A4490 contains three fixed frequency, buck switching con- verters with peak current-mode control, including slope compen- sation. Each converter can be independently turned on and off via the enable inputs (EN1, EN2, and EN3), which are ...
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A4490 VBB 0V VBB+VCP VREG1 VREG2 VREG3 PORZ Figure 1. Timing diagram for powering up and down using the VBB pin VBB 0V ENB1 ENB2 ENB3 VREG1 85%FB1 VREG2 VREG3 PORZ SS Figure 2. Timing diagram for ...
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A4490 When the V voltage starts to fall below the undervoltage warn- BB ing level 3.6 V typical, the PORZ flag resets. BBUV(por) This gives advance warning to the system controller that the V voltage is falling. ...
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A4490 The bias current flowing out of the FB1 node into R2, will BIAS introduce a small voltage offset to the output. Enable Each regulator channel can be individually enabled via the corresponding ENBx pin. If any channel ...
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A4490 The maximum peak-to-peak ripple current, I maximum input voltage. Therefore the duty cycle, D, should be found under these conditions (for the VREG1 channel REG1 f D(min) = (max)+ where V is the forward voltage ...
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A4490 Again, there is generally no need to consider the heating effects of the rms current flowing through the ESR. Also, the phase- shifting of the input current drawn by each of the regulators helps to reduce the overall rms ...
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A4490 Switch Dynamic Losses The following can be used to deter- mine switch dynamic losses: Both turn on and turn off losses can be estimated: I LOAD = 30 10 (min DYN 2 where f is the ...
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A4490 This calculation assumes no thermal influence from other compo- nents. If possible advisable to mount the flyback diodes on the reverse side of the printed circuit board. Ensure low imped- ance electrical connections are implemented between board ...
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A4490 The VBB terminals for V and V REG1 REG2 via short and wide traces to the VBB terminal for V • Each inductor should be connected as close as possible to the respective switching FET (LX1, LX2, and LX3) ...
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A4490 4.00 ±0. 21X 0.08 C +0.05 0.25 –0.07 0.50 +0.15 0.40 –0. 2.60 Copyright ©2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or ...