ISL6551IBZ-T Intersil, ISL6551IBZ-T Datasheet
ISL6551IBZ-T
Specifications of ISL6551IBZ-T
Related parts for ISL6551IBZ-T
ISL6551IBZ-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL6551 ...
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... Ordering Information PART TEMP NUMBER RANGE (°C) PACKAGE ISL6551IB SOIC ISL6551IBZ (Note SOIC (Pb-free) M28.3 ISL6551IR 6x6 QFN ISL6551IRZ (Note 6x6 QFN (Pb-free) ISL6551ABZ (Note) -40 to 105 28 Ld SOIC (Pb-free) M28.3 ISL6551AR -40 to 105 28 Ld 6x6 QFN ISL6551ARZ (Note) -40 to 105 ...
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Functional Pin Description PACKAGE PIN # SOIC QFN PIN SYMBOL 1 26 VSS R_RESDLY 5 2 R_RA 6 3 ISENSE 7 4 PKILIM 8 5 BGREF 9 6 R_LEB 10 7 CS_COMP ...
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Functional Block Diagram BANDGAP REFERENCE BGREF 8 7 PKILIM R_LEB 9 RESODLY RESODLY R_RESDLY 4 ISENSE 6 RAMP RAMP ADJUST ADJUST R_RA CLOCK 3 RD GENERATOR ERROR AMP (See Fig. 4) EAO 14 13 EAI DC OK ...
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Absolute Maximum Ratings Supply Voltage VDD, VDDP1, VDDP2 . . . . . . . . . . . . . . -0.3 to 16V Enable Inputs (ON/OFF, LATSD ...
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Electrical Specifications These specifications apply for VDD = VDDP = 12V and T (ISL6551AB), Unless Otherwise Stated (Continued) PARAMETER SYMBOL PWM DELAYS (Note 4) LOW1,2 delay “Rising” LOW1,2 delay “Falling” SYNC1,2 delay “Falling” SYNCF SYNC1,2 delay “Rising” SYNCR ERROR AMPLIFIER ...
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Electrical Specifications These specifications apply for VDD = VDDP = 12V and T (ISL6551AB), Unless Otherwise Stated (Continued) PARAMETER SYMBOL Vsat_sinking (ISL6551IB) Vsat_low Vsat_sinking (ISL6551AB) Vsat_low SYNCHRONOUS SIGNALS (SYNC1, SYNC2) Maximum capacitive load (each) PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4) ...
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Drive Signals Timing Diagrams CLOCK UPPER1 UPPER2 SYNC1 SYNC2 LOWER1 I LOWER1 LOWER2 I LOWER2 RAMP ADJUST OUTPUT TO PWM LOGIC T1 NOTES Leading edge blanking Resonant delay dead time ...
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Shutdown Timing Diagrams LATSD ON/OFF A VDD PKILIM > BGREF ILIM_OUT PKILIM < BGREF SOFT START DRIVER ENABLE SOFT-START SHUTDOWN FAULT OFF Shutdown Timing Descriptions A (ON/OFF) - When the ON/OFF is pulled low, the soft-start capacitor is discharged and ...
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Block/Pin Functional Descriptions Detailed descriptions of each individual block in the functional block diagram on page 3 are included in this section. Application information and design considerations for each pin and/or each block are also included. • IC Bias Power ...
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CT (pF) RECOMMENDED RANGE FIGURE FREQUENCY - Note that the capacitance of a scope probe (~12pF for single ended) would induce a smaller frequency ...
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... The UVLO holds all the drivers low until the VDD has reached the turn-on threshold VDD - The upper drivers require assistance of external level- shifting circuits such as Intersil’s HIP2100 or pulse transformers to drive the upper power switches of a bridge converter. • Peak Current Limit (PKILIM) ...
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R_RESDLY (kΩ) FIGURE 7. R_RESDLY vs RESDLY • Leading Edge Blanking (R_LEB current mode control, the sensed switch (FET) current is processed ...
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Ramp Adjust (R_RA, ISENSE) - The ramp adjust block adds an offset component (200mV) and a slope adjust component to the ISENSE signal before processing it at the PWM Logic block, as shown in Figure 9. This ensures that ...
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Power Good (DCOK) - DCOK pin is an open drain output capable of sinking 5mA low when the output voltage is within the UVOV window. The static regulation limit is ± the 5% is the dynamic regulation ...
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Additional Applications Information Table 1 highlights parameter setting for the ISL6551. Designers can use this table as a design checklist. For TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST VDD = 12V at room temperature, unless otherwise stated. PARAMETER PIN NAME Frequency Dead ...
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Figure 13 shows the block diagram of a power supply system employing the ISL6551 full bridge controller. The ISL6551 not only is a full bridge PWM controller but also can be used as a push-pull PWM controller. Users can design ...
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Current Sense T_CURRENT Q3_S Q4_S FIGURE 14A. TWO-LEG SENSE CURRENT_SEN_P FIGURE 14B. TOP SENSE Q3_S & Q4_S RSENSE FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL) Two-Leg Sense - Senses the current that flows through both lower primary FETs. ...
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Feedback EAI VOPOUT FIGURE 16A. SECONDARY CONTROL VREF = 5V VOPOUT IL207 TL431 FIGURE 16B. PRIMARY CONTROL Secondary Control - In secondary side control systems, only a few resistors and capacitors are required to complete the feedback loop. Primary Control ...
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... The secondary winding carries all the load, i.e., all the load is reflected to the primary. 20 ISL6551 Supervisor Circuits (1) INTEGRATED SOLUTION • Intersil ISL6550 Supervisor And Monitor (SAM). Its QFN package requires less space than the SOIC package. VOPOUT VREF5 F OUT BDAC • ...
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Output Filter L S+ OUT S– FIGURE 20A. CURRENT DOUBLER FILTER L OUT V F OUT F CLOCK FIGURE 20B. CONVENTIONAL FILTER Current Doubler Filter - Two inductors are needed, but they can be integrated and coupled into one core. ...
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Primary FET Drivers (1) PUSH-PULL DRIVERS LOWER1 LOWER2 FIGURE 23A. PUSH-PULL MEDIUM CURRENT DRIVERS Push-Pull Medium Current Drivers - Upper drivers are not used. No external drivers are required. Secondary control. Operate at the switching frequency. Push-Pull High Current Drivers ...
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... Full Bridge Primary Control - Lower drivers can directly drive the power switches, while upper drivers require the assistance of level-shifting circuits such as a pulse transformer or Intersil’s HIP2100 half-bridge driver. External high current drivers are not required in medium power applications, but level-shifting circuits are still required for upper drivers ...
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Simplified Typical Application Schematics SB+12V UPPER1 UPPER2 LOWER1 LOWER2 SA+12V + OUT - PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 LED SHARE BUS 200W TELECOMMUNICATION POWER SUPPLY (SEE AN1002 FOR DETAILS) SB+48V VDD LO HB VSS ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...