ISL6615ACBZ-T Intersil, ISL6615ACBZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL6615ACBZ-T
• Description: IC MOSFET DRVR SYNC HF 6A 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6615ACBZ-T

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 2.5A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

thermal vias. This combination of vias for vertical heat
escape, extended copper plane, and buried planes for
heat spreading allows the IC to achieve its full thermal
potential.
Upper MOSFET Self Turn-On Effects at
Start-up
Should the driver have insufficient bias voltage applied,
its outputs are floating. If the input bus is energized at a
high dV/dt rate while the driver outputs are floating due
to the self-coupling via the internal C
the UGATE could momentarily rise up to a level greater
than the threshold voltage of the MOSFET. This could
potentially turn on the upper switch and result in
damaging inrush energy. Therefore, if such a situation
(when input bus powered up before the bias of the
controller and driver is ready) could conceivably be
encountered, it is a common practice to place a resistor
(R
MOSFET to suppress the Miller coupling effect. The value
of the resistor depends mainly on the input voltage’s rate
of rise, the C
threshold of the upper MOSFET. A higher dV/dt, a lower
C
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications,
the integrated 20kΩ typically sufficient, not affecting
normal performance and efficiency.
The coupling effect can be roughly estimated with the
formulas in Equation 5, which assume a fixed linear input
ramp and neglect the clamping effect of the body diode
DS
UGPH
/C
GS
) across the gate and source of the upper
ratio, and a lower gate-source threshold upper
GD
/C
GS
ratio, as well as the gate-source
9
GD
of the MOSFET,
ISL6615A
of the upper drive and the bootstrap capacitor. Other
parasitic components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
V
R
GS_MILLER
FIGURE 5. GATE-TO-SOURCE RESISTOR TO REDUCE
=
PVCC
R
UGPH
=
+
UPPER MOSFET MILLER COUPLING
R
DU
DL
dV
------- R C
dt
GI
⋅
⋅
C
rss
rss
BOOT
PHASE
⎛
⎜
⎜
⎜
⎜
⎝
1 e
UGATE
C
=
BOOT
–
C
--------------------------------- -
dV
------ - R C
GD
dt
G
–
⋅
V
DS
⋅
R
iss
C
GI
GD
C
⎞
⎟
⎟
⎟
⎟
⎠
iss
C
GS
=
S
C
VIN
GD
April 22, 2010
Q
UPPER
D
+
(EQ. 5)
C
FN6608.1
C
DS
GS