ISL6615ACBZ-T Intersil, ISL6615ACBZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL6615ACBZ-T
• Description: IC MOSFET DRVR SYNC HF 6A 8-SOIC
• Manufacturer: Intersil

Specifications of ISL6615ACBZ-T

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 10.0ns
• Current - Peak: 2.5A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 6.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; N
and N
respectively; PVCC is the drive voltage for both upper
and lower FETs. The IQ*VCC product is the quiescent
power of the driver without capacitive load and is
typically 200mW at 300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among
the resistive components along the transition path. The
drive resistance dissipates a portion of the total gate
drive power losses, the rest will be dissipated by the
external gate resistors (R
gate resistors (R
and 4 show the typical upper and lower gate drives
turn-on transition path. The power dissipation on the
driver can be roughly estimated, as shown in Equation 4.
P
P
P
P
R
I
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON
DR
Qg_TOT
DR
DR_UP
DR_LOW
EXT1
P
P
=
PVCC
=
Qg_Q2
Qg_Q1
Q2
⎛
⎜
⎝
P
=
Q
-----------------------------------------------------
DR_UP
=
G1
=
R
are the number of upper and lower MOSFETs,
=
⎛
⎜
⎝
G1
P
PHASE
--------------------------------------
R
•
=
⎛
⎜
⎝
=
Qg_Q1
PATH
HI1
--------------------------------------
R
PVCC N
V
+
Q
-------------------------------------- - F
Q
-------------------------------------- - F
HI2
BOOT
+
GS1
R
R
-------------
R
N
G2
R
G1
+
P
HI1
GI1
HI1
Q1
LO1
GI1
R
R
+
V
DR_LOW
V
•
HI2
+
•
GS2
EXT1
R
GS1
•
PVCC
PVCC
P
EXT2
and R
Qg_Q2
Q1
+
+
2
+
2
+
--------------------------------------- -
R
G1
G1
Q
-----------------------------------------------------
•
I
•
GI2
LO1
--------------------------------------- -
R
+
Q
R
8
G2
LO2
EXT2
I
and R
•
SW
Q
SW
R
and Q
R
) of MOSFETs. Figures 3
VCC
•
+
LO1
G1
R
•
PVCC N
+
G
V
R
LO2
VCC
•
•
N
GS2
EXT1
R
N
=
R
G2
EXT2
Q2
C
Q1
G2
GS1
R
GI1
GD
G2
C
) and the internal
•
⎞
⎟
⎠
) is defined at a
GS
•
⎞
⎟
⎠
and V
+
Q2
P
---------------------
•
R
-------------
Qg_Q1
N
P
---------------------
S
⎞
⎟
⎠
GI2
Q2
Qg_Q2
2
•
2
F
GS2
D
SW
Q1
C
) in the
+
DS
(EQ. 2)
(EQ. 3)
(EQ. 4)
I
Q
ISL6615A
Q1
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs)
can cause serious ringing, exceeding the absolute
maximum ratings of the devices. A good layout helps
reduce the ringing on the switching node (PHASE) and
significantly lower the stress applied to the output drives.
The following advice is meant to lead to an optimized
layout and performance:
• Keep decoupling loops (VCC-GND, PVCC-GND and
• Minimize trace inductance, especially on low-
• Shorten all gate drive loops (UGATE-PHASE and
• Minimize the inductance of the PHASE node. Ideally,
• Minimize the current loop of the output and input
• Avoid routing relatively high impedance nodes (such
In addition, for heat spreading, place copper underneath
the IC whether it has an exposed pad or not. The copper
area can be extended beyond the bottom area of the IC
and/or connected to buried power ground plane(s) with
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON
BOOT-PHASE) short and wide (at least 25 mils). Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane
with at least two vias.
impedance lines. All power traces (UGATE, PHASE,
LGATE, GND, PVCC, VCC, GND) should be short and
wide (at least 25 mils). Try to place power traces on
a single layer, otherwise, two vias on interconnection
are preferred where possible. For no connection (NC)
pins on the QFN part, connect it to the adjacent net
(LGATE2/PHASE2) can reduce trace inductance.
LGATE-GND) and route them closely spaced.
the source of the upper and the drain of the lower
MOSFET should be as close as thermally allowable.
power trains. Short the source connection of the
lower MOSFET to ground as close to the transistor
pin as feasible. Input capacitors (especially ceramic
decoupling) should be placed as close to the drain of
upper and source of lower MOSFETs as possible.
as PWM and ENABLE lines) close to high dV/dt
UGATE and PHASE nodes.
PVCC
R
PATH
R
HI2
LO2
R
G2
G
R
C
GI2
GD
C
GS
S
D
Q2
C
April 22, 2010
DS
FN6608.1