IR2214SSPBF International Rectifier, IR2214SSPBF Datasheet - Page 13

• Manufacturer Part Number: IR2214SSPBF
• Description: IC DRIVER HALF BRIDGE SGL 24SSOP
• Manufacturer: International Rectifier

Specifications of IR2214SSPBF

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 440ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 1200V
• Voltage - Supply: 11.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Family Hvic: General Purpose HVICs
• Channels: 2
• Topology: Half Bridge
• Application: General Purpose / Motor Control
• Voffset: 1200
• Io+ (ma): 2000
• Io- (ma): 3000
• Separate Power And Logic Ground: Yes
• Uvlo: Vcc / Vbs
• Vbsuv+ / Vccuv+ Min (v): 9.3
• Vbsuv+ / Vccuv+ Typ (v): 10.2
• Vbsuv+ / Vccuv+ Max (v): 11.4
• Vbsuv- / Vccuv- Min (v): 8.7
• Vbsuv- / Vccuv- Typ (v): 9.3
• Vbsuv- / Vccuv- Max (v): 10.3
• Dt / Sdt Min (ns): 5700
• Dt / Sdt Typ (ns): 9250
• Dt / Sdt Max (ns): 13500
• T On Min (ns): 220
• T On Typ (ns): 440
• T On Max (ns): 660
• T Off Min (ns): 220
• T Off Typ (ns): 440
• T Off Max (ns): 660
• Fault Reporting: Yes
• Package: 24 Lead
• Part Status: Active & Preferred
• Special Features: Soft Shutdown and Desaturation Detection
• For Use With: IRMD2214SS - KIT DESIGN EVAL BOARD IR2214SS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The external sensing diode should have BV > 600 V or
1200 V and low stray capacitance (in order to minimize
noise coupling and switching delays). The diode is
biased by an internal pull-up resistor R
V
dedicated circuit (see the active-bias section for IR21141
and IR22141). When V
DSH or DSL pin increases too. Being internally biased to
the local supply, the DSH/DSL voltage is automatically
clamped.
threshold, the comparator triggers (see Fig. 13). The
comparator’s output is filtered in order to avoid false
desaturation detection by externally induced noise;
pulses shorter than t
detecting a false desaturation event during IGBT turn on,
the desaturation circuit is disabled by a blanking signal
(T
estimated maximum IGBT turn on time and must be not
exceeded by proper gate resistance sizing. When the
IGBT is not completely saturated after T
is detected and the driver will turn off.
www.irf.com
CC
BL
/I
, see blanking block in Fig. 13). This time is the
DS-
or V
When
BS
/I
DesatHS/LS
DS-
on/off
DSH/DSL
for IR2114 or IR2214) or by a
(external hard
FAULT/SD
shutdown)
SY_FLT
(external
FLTCLR
CE
DS
hold)
increases, the voltage at the
are filtered out. To avoid
One Shot
tss
exceeds
Figure 13: High and Low Side Output Stage
P
P
Blanking
Figure 14: Fault Management Diagram
r
internal
r
filter
e
e
t
t
HOLD
BL
DS
D
D
BL
r
r
i
DSH/L
i
v
v
e
e
, desaturation
r
r
the
(equal to
internal FAULT
(hard shutdown)
V
DESAT+
comparator
desat
SHOT
(t
ONE
on
1)
V
DESAT
Eligible desaturation signals initiate the SSD sequence.
While in SSD, the driver’s output goes to a high
impedance state and the SSD pull-down is activated to
turn off the IGBT through the SSDH/SSDL pin. The
SY_FLT output pin (active low, see Fig. 14) reports the
gate driver status during the SSD sequence (t
the SSD has finished, SY_FLT releases, and the gate
driver generates a FAULT signal (see the FAULT/SD
section) by activating the FAULT/SD pin. This generates
a hard shutdown for both the high and low output stages
(HO=LO=low). Each driver is latched low until the fault is
cleared (see FLT_CLR).
Figure 14 shows the fault management circuit. In this
diagram DesatHS and DesatLS are two internal signals
that come from the output stages (see Fig. 13).
It must be noted that while in SSD, both the
undervoltage fault and external SD are masked until the
end of SSD. Desaturation protection is working
independently by the other control pin and it is disabled
only when the output status is off.
Q
Q
SET
CLR
R
S
IR211(4,41)/IR221(4,41)SSPbF
VB/Vcc
HOPH/L
HONH/L
SSDH/L
DSH/L
VS/COM
sensing
diode
DesatHS
DesatLS
UVCC
SS
). Once
13