MAX6955ATL+ Maxim Integrated Products, MAX6955ATL+ Datasheet - Page 12
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MAX6955ATL+
Manufacturer Part Number
MAX6955ATL+
Description
IC DRVR DSPL LED 40-TQFN
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX6955AAX.pdf
(43 pages)
Specifications of MAX6955ATL+
Display Type
LED
Configuration
7, 14, 16 Segment
Interface
I²C
Current - Supply
22mA
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Number Of Digits
16
Number Of Segments
128
Low Level Output Current
935 mA
High Level Output Current
55 mA
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Supply Current
30 mA
Maximum Power Dissipation
2051.3 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
Details
2-Wire Interfaced, 2.7V to 5.5V LED Display
Driver with I/O Expander and Key Scan
range. The first 16 characters of the 16-segment ROM
map cover 7-segment displays. These 16 characters
are numeric 0 to 9 and characters A to F (i.e., the hexa-
decimal set).
The OSC pin can be fitted with capacitor C
use the internal RC multiplex oscillator, or driven by an
external clock to set the multiplex clock frequency and
blink rate. The multiplex clock frequency determines the
frequency that the complete display is updated. With
OSC at 4MHz, each display digit is enabled for 200µs.
The internal RC oscillator uses an external resistor,
R
lator frequency. The suggested values of R
and C
makes the blink frequency 0.5Hz or 1Hz.
The external clock is not required to have a 50:50 duty
cycle, but the minimum time between transitions must
be 50ns or greater and the maximum time between
transitions must be 750ns.
The on-chip oscillator may be accurate enough for
applications using a single device. If an exact blink rate
is required, use an external clock ranging between
1MHz and 8MHz to drive OSC. The OSC inputs of multi-
ple MAX6955s can be connected to a common external
clock to make the devices blink at the same rate. The
relative blink phasing of multiple MAX6955s can be syn-
chronized by setting the T bit in the control register for
all the devices in quick succession. If the serial inter-
faces of multiple MAX6955s are daisy-chained by con-
necting the DOUT of one device to the DIN of the next,
then synchronization is achieved automatically by
updating the configuration register for all devices simul-
taneously. Figure 10 is the multiplex timing diagram.
The OSC_OUT output is a buffered copy of either the
internal oscillator clock or the clock driven into the OSC
pin if the external clock has been selected. The feature
is useful if the internal oscillator is used, and the user
wishes to synchronize other MAX6955s to the same
blink frequency. The oscillator is disabled while the
MAX6955 is in shutdown.
The scan-limit register sets how many 14-segment dig-
its or 16-segment digits or pairs of 7-segment digits are
displayed, from 1 to 8. A bicolor digit is connected as
two monocolor digits. The scan register also limits the
number of keys that can be scanned.
Since the number of scanned digits affects the display
brightness, the scan-limit register should not be used to
12
SET
______________________________________________________________________________________
, and an external capacitor, C
SET
(22pF) set the oscillator at 4MHz, which
Multiplex Clock and Blink Timing
Scan-Limit Register
SET
OSC_OUT Output
, to set the oscil-
SET
SET
to GND to
(56kΩ)
blank portions of the display (such as leading-zero sup-
pression). Table 26 shows the scan-limit register format.
Digital control of display brightness is provided and
can be managed in one of two ways: globally or individ-
ually. Global control adjusts all digits together.
Individual control adjusts the digits separately.
The default method is global brightness control, which
is selected by clearing the global intensity bit (I data bit
D6) in the configuration register. This brightness setting
applies to all display digits. The pulse-width modulator
is then set by the lower nibble of the global intensity
register, address 0x02. The modulator scales the aver-
age segment current in 16 steps from a maximum of
15/16 down to 1/16 of the peak current. The minimum
interdigit blanking time is set to 1/16 of a cycle. When
using bicolor digits, 256 color/brightness combinations
are available.
Individual brightness control is selected by setting the
global intensity bit (I data bit D6) in the configuration
register. The pulse-width modulator is now no longer
set by the lower nibble of the global intensity register,
address 0x02, and the data is ignored. Individual digital
control of display brightness is now provided by a sep-
arate pulse-width modulator setting for each digit. Each
digit is controlled by a nibble of one of the four intensity
registers: intensity10, intensity32, intensity54, and inten-
sity76 for all display types, plus intensity10a, intensi-
ty32a, intensity54a, and intensity76a for the extra eight
digits possible when 7-segment displays are used. The
data from the relevant register is used for each digit as
it is multiplexed. The modulator scales the average
segment current in 16 steps in exactly the same way as
global intensity adjustment.
Table 27 shows the global intensity register format. Table
28 shows individual segment intensity registers. Table 29
shows the even individual segment intensity format. Table
30 shows the odd individual segment intensity format.
The MAX6955 features five general-purpose input/out-
put (GPIO) ports: P0 to P4. These ports can be individ-
ually enabled as logic inputs or open-drain logic
outputs. The GPIO ports are not debounced when con-
figured as inputs. The ports can be read and the out-
puts set using the 2-wire interface.
Some or all of the five ports can be configured to per-
form key scanning of up to 32 keys. Ports P0 to P4 are
renamed Key_A, Key_B, Key_C, Key_D, and IRQ,
respectively, when used for key scanning. The full key-
scanning configuration is shown in Figure 11. Table 31
is the GPIO data register.
GPIO and Key Scanning
Intensity Registers