AT17C65A-10JC Atmel, AT17C65A-10JC Datasheet - Page 3

• Manufacturer Part Number: AT17C65A-10JC
• Description: IC SER CONFIG PROM 65K 20PLCC
• Manufacturer: Atmel

Specifications of AT17C65A-10JC

• Programmable Type: Serial EEPROM
• Memory Size: 64kb
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT17C65A10JC

FPGA Device
Configuration
0996D–08/01
This document discusses the EPF8K and EPF10K device interfaces. For more details or
information on other Altera applications, please reference the “AT17A Series Conver-
sions from Altera FPGA Serial Configuration Memories” application note.
FPGA devices can be configured with a low-density AT17A Series EEPROM (see
Figure 1 and Figure 2). The AT17A Series device stores configuration data in its
EEPROM array and clocks the data out serially according to an external clock source.
The OE, nCS and DCLK pins supply the control signals for the address counter and the
output tri-state buffer. The AT17A Series device sends a serial bitstream of configura-
tion data to its DATA pin, which is connected to the DATA0 input pin on the FPGA
device.
When configuration data for an FPGA device exceeds the capacity of a single AT17A
Series device, multiple AT17A Series devices can be serially linked together (see
Figure 2). When multiple AT17A Series devices are required, the nCASC and nCS pins
provide handshaking between the cascaded EEPROMs.
Note:
The first AT17A Series Configurator (whose nCS input is directly driven by the FPGA)
provides the first stream of data to the FPGA device during multi-device configuration.
Once the first AT17A Series device finishes sending configuration data, it drives its
nCASC pin Low, which drives the nCS pin of the second AT17A Series device Low. This
allows the second AT17A Series device to send configuration data to the FPGA.
If the nCS pin on the first AT17A Series device is driven High before all configuration
data is transferred, or if nCS is not driven High after all configuration data is transferred,
nSTATUS is driven Low, indicating a configuration error.
The low density AT17A Series Configuration EEPROMs are not designed to act as sys-
tem masters (i.e., provide clock pulses on the serial bus to other devices). Clocking
must be supplied by an FPGA device, a high-density AT17A Series device (see
Figure 3), or an external oscillator.
A single AT17C/LV65A may only be used at the end of a cascade chain or as a stand-
alone device.
AT17C/LV65A/128A/256A
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