AT17C65-10NC Atmel, AT17C65-10NC Datasheet
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AT17C65-10NC
Specifications of AT17C65-10NC
Related parts for AT17C65-10NC
AT17C65-10NC Summary of contents
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... Low-power Standby Mode Description The AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con- figuration memory for Field Programmable Gate Arrays. The low-density AT17 Series is packaged in the 8-pin PDIP, 8-lead SOIC, and the popular 20-lead PLCC and SOIC ...
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Block Diagram POWER ON RESET FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associ- ated interconnections are established by a configuration program. The program is loaded either automatically upon power-up command, ...
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... Standby Mode The AT17C/LV65/128/256 enters a low-power standby mode whenever CE is asserted High. In this mode, the Configurator consumes less than 75 µA of current at 5.0V. The output remains in a high impedance state regardless of the state of the OE input. AT17C65/128/256 AT17LV65/128/256 VCC DATA SER_EN CLK RESET/OE CE cascade chain ...
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Pin Configurations 20 8 PLCC/ DIP/ SOIC SOIC Pin Pin Name 2 1 DATA 4 2 CLK 6 3 RESET/ GND 14 6 CEO SER_EN 20 8 VCC Absolute Maximum Ratings* ...
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Operating Conditions Symbol Description Supply voltage relative to GND Commercial -0°C to +70°C Supply voltage relative to GND V Industrial CC -40°C to +85°C Supply voltage relative to GND Military -55°C to +125°C AT17CXXX AT17LVXXX Min/Max Min/Max 4.75/5.25 3.0/3.6 4.5/5.5 ...
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DC Characteristics = 5V ± 5% Commercial/5V ± 10% Ind./Mil Symbol Description V High-level input voltage IH V Low-level input voltage IL V High-level output voltage ( Low-level output voltage ( High-level output voltage ...
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AC Characteristics CE RESET/OE CLK T CE DATA AC Characteristics When Cascading RESET/OE CE CLK T LAST BIT DATA T CEO T SCE CAC CDF OCK T OCE T SCE T HCE T ...
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... AC Characteristics for AT17C65/128 = 5V ± 5% Commercial ± 10% Ind./Mil Symbol Description ( Data Delay OE ( Data Delay CE (2) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK OH ( Data Float Delay DF T CLK Low Time LC T CLK High Time Setup Time to CLK (to guarantee proper counting) ...
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AC Characteristics for AT17C256 ±5% Commercial ± 10% Ind./Mil Symbol Description ( Data Delay OE ( Data Delay CE (2) T CLK to Data Delay CAC T ...
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AC Characteristics for AT17LV65/128/256 = 3.3V ± 10 Symbol Description ( Data Delay OE ( Data Delay CE (2) T CLK to Data Delay CAC T Data Hold from CE, OE, or ...
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... Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Ordering Code AT17C65-10PC AT17C65-10NC AT17C65-10JC AT17C65-10SC AT17C65-10PI AT17C65-10NI AT17C65-10JI AT17C65-10SI AT17C128-10PC AT17C128-10NC ...
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Ordering Information – 3.3V Devices Memory Size 64K AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI 128K AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI 256K AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI 8P3 8-pin, 0.300" Wide, Plastic Dual ...
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Packaging Information 8P3, 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) PIN 1 .300 (7.62) REF .210 (5.33) MAX .100 (2.54) BSC SEATING PLANE .150 (3.81) .115 ...
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