W9425G6EH-5 Winbond Electronics, W9425G6EH-5 Datasheet - Page 4
![IC DDR-400 SDRAM 256MB 66TSSOPII](/photos/28/21/282152/w9425g6eh-5_sml.jpg)
W9425G6EH-5
Manufacturer Part Number
W9425G6EH-5
Description
IC DDR-400 SDRAM 256MB 66TSSOPII
Manufacturer
Winbond Electronics
Datasheet
1.W9425G6EH-5.pdf
(54 pages)
Specifications of W9425G6EH-5
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
256M (16Mx16)
Speed
250MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOPII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W9425G6EH-5
Manufacturer:
WINBOND
Quantity:
1 728
Part Number:
W9425G6EH-5
Manufacturer:
WINBOND/华邦
Quantity:
20 000
1. GENERAL DESCRIPTION
W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. W9425G6EH delivers a data bandwidth
of up to 500M words per second (-4). To fully comply with the personal computer industrial standard,
W9425G6EH is sorted into the following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the
DDR500/CL3 and CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I
grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5
specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9425G6EH is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5V ±0.2V Power Supply for DDR333/400
2.6V ±0.1V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
7.8µS refresh interval (8K/64 mS refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
- 4 -
Publication Release Date:Dec. 03, 2008
W9425G6EH
Revision A08