CY7C019V-20AXC Cypress Semiconductor Corp, CY7C019V-20AXC Datasheet - Page 12

• Manufacturer Part Number: CY7C019V-20AXC
• Description: IC SRAM 1.152MBIT 20NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C019V-20AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1.152M (128K x 9)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 1.125Mb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 175mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 9b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-06044 Rev. *C
Switching Waveforms
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
Busy Timing Diagram No. 1 (CE Arbitration)
CE
CE
Right Address Valid First:
Note:
37. If t
L
ADDRESS
ADDRESS
R
Valid First:
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Valid First:
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
BUSY
BUSY
BUSY
BUSY
CE
CE
CE
CE
L,R
L,R
R
R
R
R
L
L
L
L
R
R
L
L
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
t
t
[37]
BLA
BLA
ADDRESS MATCH
ADDRESS MATCH
[37]
t
t
BLC
BLC
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C008V/009V
CY7C018V/019V
Page 12 of 18
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