LH28F160S5T-L70A Sharp Microelectronics, LH28F160S5T-L70A Datasheet - Page 21

• Manufacturer Part Number: LH28F160S5T-L70A
• Description: IC FLASH 16MBIT 70NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160S5T-L70A

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-TSOP
• Other names: 425-1840; LHF16KA9

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4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations With WP#=V
individual block lock-bits can be set using the Set
Block Lock-Bit command. See Table 13 for a
summary of hardware and software write protection
options.
Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 12). The CPU can detect the completion
of the set block lock-bit event by analyzing the STS
pin output or status register bit SR.7.
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations occur
only when V
absence of this high voltage, block lock-bit contents
are protected against alteration.
A successful set block lock-bit operation requires
WP#=V
SR.4 will be set to "1" and the operation will fail. Set
block lock-bit operations with WP#<V
spurious results and should not be attempted.
4.13 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP#=V
IH
. If it is attempted with WP#=V
CC
=V
CC1/2
and V
PP
=V
PPH1
IL
IH
, SR.1 and
. In the
produce
LHF16KA9
IH
IH
,
,
block lock-bits can be cleared using only the Clear
Block Lock-Bits command. See Table 13 for a
summary of hardware and software write protection
options.
Clear block lock-bits operation is executed by a two-
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 13). The CPU can detect
completion of the clear block lock-bits event by
analyzing the STS Pin output or status register bit
SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when
V
operation is attempted while V
SR.5 will be set to "1". In the absence of this high
voltage, the block lock-bits content are protected
against alteration. A successful clear block lock-bits
operation requires WP#=V
WP#=V
operation will fail. Clear block lock-bits operations
with V
not be attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
CC
PP
=V
or V
IH
CC1/2
IL
<RP# produce spurious results and should
, SR.1 and SR.5 will be set to "1" and the
CC
and V
transitioning out of valid range or RP#
PP
=V
PPH1
IH
. If a clear block lock-bits
. If it is attempted with
PP
≤V
PPLK
, SR.3 and
Rev. 2.0
18